mirror of
https://github.com/RetroDECK/Supermodel.git
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Fixed warnings and whitespace
This commit is contained in:
Bart Trzynadlowski
parent
f0488a3c94
commit
bd09b3b68b
7638
Src/CPU/Z80/Z80.cpp
7638
Src/CPU/Z80/Z80.cpp
File diff suppressed because it is too large
Load diff
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@ -27,17 +27,17 @@
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*
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* Known inaccuracies:
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*
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* - Interrupts are accepted immediately after EI instruction. In reality,
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* interrupts become enabled after the instruction following EI. This
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* could be implemented with a state machine in Run() if needed.
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* This feature exists to prevent interrupts from occuring before a RETI
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* instruction executes in the interrupt handler. Interrupt callbacks
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* should take care to immediately clear the interrupt line, otherwise,
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* an improperly timed interrupt may occur right after an EI instruction
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* but before the service routine has a chance to return.
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* - HALT instruction is not implemented (it just exits).
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* - 16-bit words are read as two bytes but these reads may not occur in
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* the exact same order as the real device. Needs to be checked.
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* - Interrupts are accepted immediately after EI instruction. In reality,
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* interrupts become enabled after the instruction following EI. This
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* could be implemented with a state machine in Run() if needed.
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* This feature exists to prevent interrupts from occuring before a RETI
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* instruction executes in the interrupt handler. Interrupt callbacks
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* should take care to immediately clear the interrupt line, otherwise,
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* an improperly timed interrupt may occur right after an EI instruction
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* but before the service routine has a chance to return.
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* - HALT instruction is not implemented (it just exits).
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* - 16-bit words are read as two bytes but these reads may not occur in
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* the exact same order as the real device. Needs to be checked.
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*/
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#ifndef INCLUDED_Z80_H
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@ -55,14 +55,14 @@
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* supplied, and this is the only supported behavior here. The interrupt
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* callback must return one of these values when the Z80 is in mode 0.
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*/
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#define Z80_INT_RST_00 0xC7 // RST 0x00 (jumps to 0x0000)
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#define Z80_INT_RST_08 0xCF // RST 0x08 (jumps to 0x0008)
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#define Z80_INT_RST_10 0xD7 // RST 0x10 (...)
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#define Z80_INT_RST_18 0xDF // RST 0x18
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#define Z80_INT_RST_20 0xE7 // RST 0x20
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#define Z80_INT_RST_28 0xEF // RST 0x28
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#define Z80_INT_RST_30 0xF7 // RST 0x30
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#define Z80_INT_RST_38 0xFF // RST 0x38
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#define Z80_INT_RST_00 0xC7 // RST 0x00 (jumps to 0x0000)
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#define Z80_INT_RST_08 0xCF // RST 0x08 (jumps to 0x0008)
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#define Z80_INT_RST_10 0xD7 // RST 0x10 (...)
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#define Z80_INT_RST_18 0xDF // RST 0x18
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#define Z80_INT_RST_20 0xE7 // RST 0x20
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#define Z80_INT_RST_28 0xEF // RST 0x28
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#define Z80_INT_RST_30 0xF7 // RST 0x30
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#define Z80_INT_RST_38 0xFF // RST 0x38
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#ifdef SUPERMODEL_DEBUGGER
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// Extra interrupt types
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@ -99,7 +99,9 @@
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#define Z80_REG16_DE_ 11
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#define Z80_REG16_HL_ 12
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class Debugger::CZ80Debug;
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namespace Debugger {
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class CZ80Debug;
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}
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#endif // SUPERMODEL_DEBUGGER
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/*
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@ -110,229 +112,228 @@ class Debugger::CZ80Debug;
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class CZ80
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{
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public:
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/*
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* Run(numCycles):
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*
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* Runs the Z80 for the specified number of instruction cycles.
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*
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* Parameters:
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* numCycles Number of instruction cycles to execute.
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*
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* Returns:
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* Number of instruction cycles actually executed.
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*/
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int Run(int numCycles);
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/*
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* TriggerNMI(void):
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*
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* Triggers a non-maskable interrupt. This is equivalent to a high-to-low
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* transition on the NMI pin (NMI pin is triggered on falling edges). This
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* may be called while the Z80 is running. NMIs are always higher priority
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* than interrupts and are taken first.
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*/
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void TriggerNMI(void);
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/*
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* SetINT(state):
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*
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* Set or clear the interrupt request. This may be called from memory
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* handlers while the Z80 is running and should be used by interrupt
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* callbacks to clear interrupts.
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*
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* Parameters:
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* state If TRUE, this is equivalent to /INT being asserted on the
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* Z80 (INT line low, which triggers an interrupt). If FALSE,
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* this deasserts /INT (INT line high, no interrupt pending).
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*/
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void SetINT(bool state);
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/*
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* Run(numCycles):
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*
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* Runs the Z80 for the specified number of instruction cycles.
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*
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* Parameters:
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* numCycles Number of instruction cycles to execute.
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*
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* Returns:
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* Number of instruction cycles actually executed.
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*/
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int Run(int numCycles);
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/*
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* TriggerNMI(void):
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*
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* Triggers a non-maskable interrupt. This is equivalent to a high-to-low
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* transition on the NMI pin (NMI pin is triggered on falling edges). This
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* may be called while the Z80 is running. NMIs are always higher priority
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* than interrupts and are taken first.
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*/
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void TriggerNMI(void);
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/*
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* SetINT(state):
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*
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* Set or clear the interrupt request. This may be called from memory
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* handlers while the Z80 is running and should be used by interrupt
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* callbacks to clear interrupts.
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*
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* Parameters:
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* state If TRUE, this is equivalent to /INT being asserted on the
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* Z80 (INT line low, which triggers an interrupt). If FALSE,
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* this deasserts /INT (INT line high, no interrupt pending).
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*/
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void SetINT(bool state);
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/*
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* GetPC(void):
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*
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* Returns the current PC value.
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*
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* Returns:
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* Current value of PC register.
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*/
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UINT16 GetPC(void);
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/*
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* GetPC(void):
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*
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* Returns the current PC value.
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*
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* Returns:
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* Current value of PC register.
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*/
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UINT16 GetPC(void);
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#ifdef SUPERMODEL_DEBUGGER
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/*
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* GetReg8(reg8):
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*
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* Reads an 8-bit register.
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*
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* Parameters:
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* reg8 Register number (use Z80_REG8_* macros).
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*
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* Returns:
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* Value of given 8-bit register.
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*/
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UINT8 GetReg8(unsigned reg8);
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/*
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* GetReg8(reg8):
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*
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* Reads an 8-bit register.
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*
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* Parameters:
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* reg8 Register number (use Z80_REG8_* macros).
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*
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* Returns:
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* Value of given 8-bit register.
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*/
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UINT8 GetReg8(unsigned reg8);
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/*
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* SetReg8(reg8, value):
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*
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* Sets value of given 8-bit register.
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*
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* Parameters:
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* reg8 Register number.
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* value Value to write.
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*
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* Returns:
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* True if succeeded, false if invalid register.
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*/
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bool SetReg8(unsigned reg8, UINT8 value);
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/*
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* SetReg8(reg8, value):
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*
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* Sets value of given 8-bit register.
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*
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* Parameters:
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* reg8 Register number.
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* value Value to write.
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*
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* Returns:
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* True if succeeded, false if invalid register.
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*/
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bool SetReg8(unsigned reg8, UINT8 value);
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/*
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* GetReg16(reg16, value):
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*
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* Reads a 16-bit register.
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*
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* Parameters:
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* reg16 Register number (use Z80_REG16_* macros).
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*
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* Returns:
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* Value of given 16-bit register.
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*/
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UINT16 GetReg16(unsigned reg16);
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/*
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* GetReg16(reg16, value):
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*
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* Reads a 16-bit register.
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*
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* Parameters:
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* reg16 Register number (use Z80_REG16_* macros).
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*
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* Returns:
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* Value of given 16-bit register.
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*/
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UINT16 GetReg16(unsigned reg16);
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/*
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* SetReg16(state):
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*
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* Sets value of given 16-bit register.
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*
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* Parameters:
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* reg16 Register.
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* value Value to write.
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*
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* Returns:
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* True if succeeded, false if invalid register.
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*/
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bool SetReg16(unsigned reg16, UINT16 value);
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/*
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* SetReg16(state):
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*
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* Sets value of given 16-bit register.
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*
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* Parameters:
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* reg16 Register.
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* value Value to write.
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*
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* Returns:
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* True if succeeded, false if invalid register.
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*/
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bool SetReg16(unsigned reg16, UINT16 value);
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#endif // SUPERMODEL_DEBUGGER
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/*
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* Reset(void):
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*
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* Resets the Z80, clearing all registers and pending interrupt requests.
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*/
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void Reset(void);
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/*
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* SaveState(StateFile, name):
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*
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* Saves the CPU state to the block file.
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*
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* Parameters:
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* StateFile Block file.
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* name Name of block to create (e.g. "Main Z80"), to facilitate
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* multiple Z80 states in the same file.
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*/
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void SaveState(CBlockFile *StateFile, const char *name);
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/*
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* Reset(void):
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*
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* Resets the Z80, clearing all registers and pending interrupt requests.
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*/
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void Reset(void);
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/*
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* SaveState(StateFile, name):
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*
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* Saves the CPU state to the block file.
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*
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* Parameters:
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* StateFile Block file.
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* name Name of block to create (e.g. "Main Z80"), to facilitate
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* multiple Z80 states in the same file.
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*/
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void SaveState(CBlockFile *StateFile, const char *name);
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/*
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* LoadState(StateFile, name):
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*
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* Loads the CPU state.
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*
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* Parameters:
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* StateFile Block file.
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* name Name of block to load.
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*/
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void LoadState(CBlockFile *StateFile, const char *name);
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/*
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* LoadState(StateFile, name):
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*
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* Loads the CPU state.
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*
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* Parameters:
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* StateFile Block file.
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* name Name of block to load.
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*/
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void LoadState(CBlockFile *StateFile, const char *name);
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/*
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* Init(BusPtr, INTF):
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*
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* One-time initialization of the Z80 emulator. Must be called first.
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*
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* A bus object must be supplied which will be used to handle all memory
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* and IO accesses. The Read8, Write8, IORead8, and IOWrite8 members need
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* to be defined. Addresses are automatically clamped to 16 bits for memory
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* and 8 bits for IO accesses.
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*
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* An interrupt callback, which is called each time an interrupt occurs,
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* should also be supplied. The interrupt callback should explicitly clear
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* the INT status (using SetINT(FALSE)) and then return the appropriate
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* vector depending on the interrupt mode that is used by the system.
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*
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* For mode 0, only Z80_INT_RST_* values are acceptable. For mode 1, the
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* return value is discarded because the Z80 will always use vector 0x0038.
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* In mode 2, an 8-bit value supplying the lower 8-bits of the interrupt
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* vector address must be returned. Bit 0 will be ignored in this case (0
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* is used).
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*
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* If a callback is not installed, the interrupt status will automatically
|
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* be cleared and interrupts will not be taken when the Z80 is in a mode
|
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* that requires vector data from the callback. In mode 1, the interrupt
|
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* callback (if one is provided) should explicitly clear the interrupt. The
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* value returned will be unused.
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*
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* Parameters:
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* BusPtr Pointer to a bus object.
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* INTF Pointer to callback function. The function accepts a
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* a pointer to the Z80 object that received the interrupt.
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*/
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void Init(CBus *BusPtr, int (*INTF)(CZ80 *Z80));
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/*
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* Init(BusPtr, INTF):
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*
|
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* One-time initialization of the Z80 emulator. Must be called first.
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*
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* A bus object must be supplied which will be used to handle all memory
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* and IO accesses. The Read8, Write8, IORead8, and IOWrite8 members need
|
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* to be defined. Addresses are automatically clamped to 16 bits for memory
|
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* and 8 bits for IO accesses.
|
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*
|
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* An interrupt callback, which is called each time an interrupt occurs,
|
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* should also be supplied. The interrupt callback should explicitly clear
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* the INT status (using SetINT(FALSE)) and then return the appropriate
|
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* vector depending on the interrupt mode that is used by the system.
|
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*
|
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* For mode 0, only Z80_INT_RST_* values are acceptable. For mode 1, the
|
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* return value is discarded because the Z80 will always use vector 0x0038.
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* In mode 2, an 8-bit value supplying the lower 8-bits of the interrupt
|
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* vector address must be returned. Bit 0 will be ignored in this case (0
|
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* is used).
|
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*
|
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* If a callback is not installed, the interrupt status will automatically
|
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* be cleared and interrupts will not be taken when the Z80 is in a mode
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* that requires vector data from the callback. In mode 1, the interrupt
|
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* callback (if one is provided) should explicitly clear the interrupt. The
|
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* value returned will be unused.
|
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*
|
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* Parameters:
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* BusPtr Pointer to a bus object.
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* INTF Pointer to callback function. The function accepts a
|
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* a pointer to the Z80 object that received the interrupt.
|
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*/
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void Init(CBus *BusPtr, int (*INTF)(CZ80 *Z80));
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#ifdef SUPERMODEL_DEBUGGER
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/*
|
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* AttachDebugger(DebugPtr):
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*
|
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* Attaches debugger to CPU.
|
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*/
|
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void AttachDebugger(Debugger::CZ80Debug *DebugPtr);
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/*
|
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* AttachDebugger(DebugPtr):
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*
|
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* Attaches debugger to CPU.
|
||||
*/
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void AttachDebugger(Debugger::CZ80Debug *DebugPtr);
|
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|
||||
/*
|
||||
* DetachDebugger():
|
||||
*
|
||||
* Detaches debugger from CPU.
|
||||
*/
|
||||
void DetachDebugger();
|
||||
/*
|
||||
* DetachDebugger():
|
||||
*
|
||||
* Detaches debugger from CPU.
|
||||
*/
|
||||
void DetachDebugger();
|
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#endif // SUPERMODEL_DEBUGGER
|
||||
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||||
/*
|
||||
* CZ80(void):
|
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* ~CZ80(void):
|
||||
*
|
||||
* Constructor and destructor.
|
||||
*/
|
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CZ80(void);
|
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~CZ80(void);
|
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/*
|
||||
* CZ80(void):
|
||||
* ~CZ80(void):
|
||||
*
|
||||
* Constructor and destructor.
|
||||
*/
|
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CZ80(void);
|
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~CZ80(void);
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private:
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// Registers
|
||||
struct GPR { // general purpose registers
|
||||
UINT16 bc;
|
||||
UINT16 de;
|
||||
UINT16 hl;
|
||||
} regs[2]; // two sets: primary (0) and alternate (1)
|
||||
UINT16 af[2]; // AF (primary and alternate)
|
||||
UINT16 ir; // interrupt vector (I) and memory refresh (R)
|
||||
UINT16 ix; // index register X
|
||||
UINT16 iy; // index register Y
|
||||
UINT16 sp; // stack pointer
|
||||
UINT16 pc; // program counter
|
||||
UINT8 iff; // interrupt flip flops (bit 1: IFF2, 0: IFF1)
|
||||
UINT8 im; // interrupt mode (0, 1, or 2 only)
|
||||
int regs_sel; // active register set (primary or alternate)
|
||||
int af_sel; // active AF
|
||||
|
||||
// Memory and IO bus
|
||||
CBus *Bus;
|
||||
|
||||
// Interrupts
|
||||
bool nmiTrigger;
|
||||
bool intLine;
|
||||
int (*INTCallback)(CZ80 *Z80);
|
||||
// Registers
|
||||
struct GPR { // general purpose registers
|
||||
UINT16 bc;
|
||||
UINT16 de;
|
||||
UINT16 hl;
|
||||
} regs[2]; // two sets: primary (0) and alternate (1)
|
||||
UINT16 af[2]; // AF (primary and alternate)
|
||||
UINT16 ir; // interrupt vector (I) and memory refresh (R)
|
||||
UINT16 ix; // index register X
|
||||
UINT16 iy; // index register Y
|
||||
UINT16 sp; // stack pointer
|
||||
UINT16 pc; // program counter
|
||||
UINT8 iff; // interrupt flip flops (bit 1: IFF2, 0: IFF1)
|
||||
UINT8 im; // interrupt mode (0, 1, or 2 only)
|
||||
int regs_sel; // active register set (primary or alternate)
|
||||
int af_sel; // active AF
|
||||
|
||||
// Memory and IO bus
|
||||
CBus *Bus;
|
||||
|
||||
// Interrupts
|
||||
bool nmiTrigger;
|
||||
bool intLine;
|
||||
int (*INTCallback)(CZ80 *Z80);
|
||||
|
||||
#ifdef SUPERMODEL_DEBUGGER
|
||||
int lastCycles;
|
||||
|
||||
Debugger::CZ80Debug *Debug;
|
||||
int lastCycles;
|
||||
Debugger::CZ80Debug *Debug;
|
||||
#endif // SUPERMODEL_DEBUGGER
|
||||
};
|
||||
|
||||
#endif // INCLUDED_Z80_H
|
||||
#endif // INCLUDED_Z80_H
|
||||
|
|
|
|||
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Reference in a new issue