Revert "port some changes from MAME/MESS"

This reverts commit b5f3d8b68e1ae62a08b00a730b6b8150758c0af3.
This commit is contained in:
toxieainc 2022-08-08 09:18:59 +02:00 committed by trzy
parent 03002d3f22
commit d4633a868d

View file

@ -2698,7 +2698,7 @@ int CZ80::Run(int numCycles)
break; break;
case 0x71: /* OUT (C),0 */ case 0x71: /* OUT (C),0 */
cycles -= cycleTables[2][0x71]; cycles -= cycleTables[2][0x71];
OUTPUT(lreg(BC), lreg(0)); OUTPUT(lreg(BC), 0);
break; break;
case 0x72: /* SBC HL,SP */ case 0x72: /* SBC HL,SP */
cycles -= cycleTables[2][0x72]; cycles -= cycleTables[2][0x72];
@ -2821,8 +2821,6 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB0]; cycles -= cycleTables[2][0xB0];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
acu = GetBYTE_pp(HL); acu = GetBYTE_pp(HL);
PutBYTE_pp(DE, acu); PutBYTE_pp(DE, acu);
@ -2834,8 +2832,6 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB1]; cycles -= cycleTables[2][0xB1];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
temp = GetBYTE_pp(HL); temp = GetBYTE_pp(HL);
op = --BC != 0; op = --BC != 0;
@ -2872,8 +2868,6 @@ int CZ80::Run(int numCycles)
case 0xB8: /* LDDR */ case 0xB8: /* LDDR */
cycles -= cycleTables[2][0xB8]; cycles -= cycleTables[2][0xB8];
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
acu = GetBYTE_mm(HL); acu = GetBYTE_mm(HL);
PutBYTE_mm(DE, acu); PutBYTE_mm(DE, acu);
@ -2885,8 +2879,6 @@ int CZ80::Run(int numCycles)
cycles -= cycleTables[2][0xB9]; cycles -= cycleTables[2][0xB9];
acu = hreg(AF); acu = hreg(AF);
BC &= 0xffff; BC &= 0xffff;
if (BC == 0)
BC = 0x10000;
do { do {
temp = GetBYTE_mm(HL); temp = GetBYTE_mm(HL);
op = --BC != 0; op = --BC != 0;
@ -3513,7 +3505,7 @@ int CZ80::Run(int numCycles)
break; break;
case 0xCB: /* CB prefix */ case 0xCB: /* CB prefix */
adr = IY + (signed char) GetBYTE_pp(pc); adr = IY + (signed char) GetBYTE_pp(pc);
//adr = adr; adr = adr;
op = GetBYTE(pc); op = GetBYTE(pc);
cycles -= cycleTables[4][op]; cycles -= cycleTables[4][op];
switch (op & 7) { switch (op & 7) {