mirror of
https://github.com/RetroDECK/Supermodel.git
synced 2024-11-25 23:25:40 +00:00
DMA and register space access for Real3D have been unified and CReal3D::ReadRegister() returns little endian data now that the PowerPC handler byte-swaps back, to be consistent with how DMA registers work.
This commit is contained in:
Bart Trzynadlowski
parent
50d1f95648
commit
f04a285727
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@ -30,6 +30,8 @@
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* in Real3D.cpp and security board-related variable was added to Model 3
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* state. PowerPC timing variables have changed. Before 0.3a release,
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* important to change format version #.
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* - Remove FLIPENDIAN32() macros and have little endian devices flip data
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* around themselves. Bus standard should be big endian.
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* - ROM sets should probably be handled with a class that manages ROM
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* loading, the game list, as well as ROM patching
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* - Wrap up CPU emulation inside a class.
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@ -833,18 +835,9 @@ void CModel3::WriteSystemRegister(unsigned reg, UINT8 data)
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DebugLog("IRQ ENABLE=%02X\n", data);
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break;
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case 0x18: // IRQ acknowledge
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{
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// MAME: Clear bits are ack. Reverse order from other IRQ regs.
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//uint8_t ack = 0;
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//for (int bit = 0; bit < 8; bit++)
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//{
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// if (!(data & (1 << bit)))
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// ack |= (1 << (7-bit));
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//}
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//IRQ.Deassert(ack);
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IRQ.Deassert(data);
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DebugLog("IRQ ACK? %02X=%02X\n", reg, data);
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break;
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}
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case 0x0C: // JTAG Test Access Port
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GPU.WriteTAP((data>>6)&1,(data>>2)&1,(data>>5)&1,(data>>7)&1); // TCK, TMS, TDI, TRST
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break;
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@ -1075,7 +1068,8 @@ UINT32 CModel3::Read32(UINT32 addr)
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// Real3D registers
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case 0x84:
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return GPU.ReadRegister(addr&0x3F);
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data = GPU.ReadRegister(addr&0x3F);
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return FLIPENDIAN32(data);
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// Real3D DMA
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case 0xC2:
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@ -145,7 +145,7 @@ void CReal3D::BeginVBlank(int statusCycles)
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// Calculate point at which status bit should change value. Currently the same timing is used for both the status bit in ReadRegister
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// and in WriteDMARegister32/ReadDMARegister32, however it may be that they are completely unrelated. It appears that step 1.x games
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// access just the former while step 2.x access the latter. It is not known yet what this bit/these bits actually represent.
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statusChange = ppc_total_cycles() + statusCycles;
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statusChange = ppc_total_cycles() + statusCycles;
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}
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void CReal3D::EndVBlank(void)
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@ -254,134 +254,6 @@ void CReal3D::EndFrame(void)
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Render3D->EndFrame();
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}
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/******************************************************************************
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DMA Device
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Register 0xC:
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-------------
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+---+---+---+---+---+---+---+---+
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|BUS|???|???|???|???|???|???|IRQ|
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+---+---+---+---+---+---+---+---+
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BUS: Busy (see von2 0x18A104) if 1.
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IRQ: IRQ pending.
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******************************************************************************/
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void CReal3D::DMACopy(void)
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{
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DebugLog("Real3D DMA copy (PC=%08X, LR=%08X): %08X -> %08X, %X %s\n", ppc_get_pc(), ppc_get_lr(), dmaSrc, dmaDest, dmaLength*4, (dmaConfig&0x80)?"(byte reversed)":"");
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//printf("Real3D DMA copy (PC=%08X, LR=%08X): %08X -> %08X, %X %s\n", ppc_get_pc(), ppc_get_lr(), dmaSrc, dmaDest, dmaLength*4, (dmaConfig&0x80)?"(byte reversed)":"");
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if ((dmaConfig&0x80)) // reverse bytes
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{
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while (dmaLength != 0)
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{
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uint32_t data = Bus->Read32(dmaSrc);
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Bus->Write32(dmaDest, FLIPENDIAN32(data));
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dmaSrc += 4;
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dmaDest += 4;
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--dmaLength;
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}
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}
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else
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{
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while (dmaLength != 0)
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{
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Bus->Write32(dmaDest, Bus->Read32(dmaSrc));
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dmaSrc += 4;
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dmaDest += 4;
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--dmaLength;
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}
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}
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}
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uint8_t CReal3D::ReadDMARegister8(unsigned reg)
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{
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switch (reg)
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{
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case 0xC: // status
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return dmaStatus;
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case 0xE: // configuration
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return dmaConfig;
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default:
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break;
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}
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DebugLog("Real3D: ReadDMARegister8: reg=%X\n", reg);
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return 0;
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}
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void CReal3D::WriteDMARegister8(unsigned reg, uint8_t data)
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{
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switch (reg)
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{
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case 0xD: // IRQ acknowledge
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if ((data&1))
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{
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dmaStatus &= ~1;
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IRQ->Deassert(dmaIRQ);
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}
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break;
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case 0xE: // configuration
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dmaConfig = data;
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break;
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default:
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DebugLog("Real3D: WriteDMARegister8: reg=%X, data=%02X\n", reg, data);
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break;
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}
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//DebugLog("Real3D: WriteDMARegister8: reg=%X, data=%02X\n", reg, data);
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}
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uint32_t CReal3D::ReadDMARegister32(unsigned reg)
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{
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switch (reg)
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{
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case 0x14: // command result
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return dmaData;
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default:
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break;
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}
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DebugLog("Real3D: ReadDMARegister32: reg=%X\n", reg);
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return 0;
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}
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void CReal3D::WriteDMARegister32(unsigned reg, uint32_t data)
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{
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switch (reg)
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{
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case 0x00: // DMA source address
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dmaSrc = data;
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break;
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case 0x04: // DMA destination address
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dmaDest = data;
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break;
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case 0x08: // DMA length
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dmaLength = data;
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DMACopy();
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dmaStatus |= 1;
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IRQ->Assert(dmaIRQ);
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break;
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case 0x10: // command register
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if ((data&0x20000000))
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{
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dmaData = 0x16C311DB; // Virtual On 2 expects this from DMA
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DebugLog("Real3D: DMA ID command issued (ATTENTION: make sure we're returning the correct value), PC=%08X, LR=%08X\n", ppc_get_pc(), ppc_get_lr());
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}
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else if ((data&0x80000000))
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{
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//dmaUnknownReg ^= 0xFFFFFFFF;
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//dmaData = dmaUnknownReg;
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dmaData = (ppc_total_cycles() >= statusChange ? 0x0 : 0xFFFFFFFF); // Not sure yet if it is just bit 2 as per ReadRegister above
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}
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break;
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case 0x14: // ?
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dmaData = 0xFFFFFFFF;
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break;
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default:
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DebugLog("Real3D: WriteDMARegister32: reg=%X, data=%08X\n", reg, data);
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break;
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}
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//DebugLog("Real3D: WriteDMARegister32: reg=%X, data=%08X\n", reg, data);
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}
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/******************************************************************************
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JTAG Test Access Port Simulation
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@ -789,6 +661,133 @@ void CReal3D::UploadTexture(uint32_t header, const uint16_t *texData)
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}
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/******************************************************************************
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DMA Device
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Register 0xC:
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-------------
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+---+---+---+---+---+---+---+---+
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|BUS|???|???|???|???|???|???|IRQ|
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+---+---+---+---+---+---+---+---+
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BUS: Busy (see von2 0x18A104) if 1.
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IRQ: IRQ pending.
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******************************************************************************/
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void CReal3D::DMACopy(void)
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{
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DebugLog("Real3D DMA copy (PC=%08X, LR=%08X): %08X -> %08X, %X %s\n", ppc_get_pc(), ppc_get_lr(), dmaSrc, dmaDest, dmaLength*4, (dmaConfig&0x80)?"(byte reversed)":"");
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//printf("Real3D DMA copy (PC=%08X, LR=%08X): %08X -> %08X, %X %s\n", ppc_get_pc(), ppc_get_lr(), dmaSrc, dmaDest, dmaLength*4, (dmaConfig&0x80)?"(byte reversed)":"");
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if ((dmaConfig&0x80)) // reverse bytes
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{
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while (dmaLength != 0)
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{
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uint32_t data = Bus->Read32(dmaSrc);
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Bus->Write32(dmaDest, FLIPENDIAN32(data));
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dmaSrc += 4;
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dmaDest += 4;
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--dmaLength;
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}
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}
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else
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{
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while (dmaLength != 0)
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{
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Bus->Write32(dmaDest, Bus->Read32(dmaSrc));
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dmaSrc += 4;
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dmaDest += 4;
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--dmaLength;
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}
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}
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}
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uint8_t CReal3D::ReadDMARegister8(unsigned reg)
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{
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switch (reg)
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{
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case 0xC: // status
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return dmaStatus;
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case 0xE: // configuration
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return dmaConfig;
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default:
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break;
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}
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DebugLog("Real3D: ReadDMARegister8: reg=%X\n", reg);
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return 0;
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}
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void CReal3D::WriteDMARegister8(unsigned reg, uint8_t data)
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{
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switch (reg)
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{
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case 0xD: // IRQ acknowledge
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if ((data&1))
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{
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dmaStatus &= ~1;
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IRQ->Deassert(dmaIRQ);
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}
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break;
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case 0xE: // configuration
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dmaConfig = data;
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break;
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default:
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DebugLog("Real3D: WriteDMARegister8: reg=%X, data=%02X\n", reg, data);
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break;
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}
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//DebugLog("Real3D: WriteDMARegister8: reg=%X, data=%02X\n", reg, data);
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}
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uint32_t CReal3D::ReadDMARegister32(unsigned reg)
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{
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switch (reg)
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{
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case 0x14: // command result
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return dmaData;
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default:
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break;
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}
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DebugLog("Real3D: ReadDMARegister32: reg=%X\n", reg);
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return 0;
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}
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void CReal3D::WriteDMARegister32(unsigned reg, uint32_t data)
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{
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switch (reg)
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{
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case 0x00: // DMA source address
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dmaSrc = data;
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break;
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case 0x04: // DMA destination address
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dmaDest = data;
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break;
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case 0x08: // DMA length
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dmaLength = data;
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DMACopy();
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dmaStatus |= 1;
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IRQ->Assert(dmaIRQ);
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break;
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case 0x10: // command register
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if ((data&0x20000000))
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{
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dmaData = 0x16C311DB; // Virtual On 2 expects this from DMA
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DebugLog("Real3D: DMA ID command issued (ATTENTION: make sure we're returning the correct value), PC=%08X, LR=%08X\n", ppc_get_pc(), ppc_get_lr());
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}
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else if ((data&0x80000000))
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{
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dmaData = ReadRegister(data & 0x3F);
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}
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break;
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case 0x14: // ?
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dmaData = 0xFFFFFFFF;
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break;
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default:
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DebugLog("Real3D: WriteDMARegister32: reg=%X, data=%08X\n", reg, data);
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break;
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}
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//DebugLog("Real3D: WriteDMARegister32: reg=%X, data=%08X\n", reg, data);
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}
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/******************************************************************************
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Basic Emulation Functions, Registers, Memory, and Texture FIFO
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******************************************************************************/
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@ -891,13 +890,15 @@ uint32_t CReal3D::ReadRegister(unsigned reg)
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DebugLog("Real3D: Read reg %X\n", reg);
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if (reg == 0)
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{
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uint32_t status = (ppc_total_cycles() >= statusChange ? 0x0 : 0x2);
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return 0xFFFFFFFD|status;
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uint32_t status = (ppc_total_cycles() >= statusChange ? 0x0 : 0x02000000);
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return 0xFDFFFFFF|status;
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}
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else
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return 0xFFFFFFFF;
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}
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// TODO: This returns data in the way that the PowerPC bus expects. Other functions in CReal3D should
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// return data this way.
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uint32_t CReal3D::ReadPCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned offset)
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{
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uint32_t d;
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