mirror of
https://github.com/RetroDECK/Supermodel.git
synced 2024-11-22 22:05:38 +00:00
452 lines
13 KiB
C++
452 lines
13 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* 68K.cpp
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*
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* 68K CPU interface. This is presently just a wrapper for the Musashi 68K core
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* and therefore, only a single CPU is supported. In the future, we may want to
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* add in another 68K core (eg., Turbo68K, A68K, or a recompiler).
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*
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* To-Do List
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* ----------
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* - Registers may not completely describe the 68K state. Musashi also has
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* additional CPU state information in the context that its MAME interface
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* accesses (interrupts pending, halted status, etc.)
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*/
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#include "68K.h"
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#include "Supermodel.h"
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#include "Musashi/m68k.h" // Musashi 68K core
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#include "Debugger/CPU/Musashi68KDebug.h"
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/******************************************************************************
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Internal Context
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An active context must be mapped before calling M68K interface functions. Only
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the bus and IRQ handlers are copied here; the CPU context is passed directly
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to Musashi.
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******************************************************************************/
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// Bus
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static IBus *s_Bus = NULL;
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#ifdef SUPERMODEL_DEBUGGER
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// Debugger
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static Debugger::CMusashi68KDebug *s_Debug = NULL;
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#endif
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// IRQ callback
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static int (*IRQAck)(int nIRQ) = NULL;
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// Cycles remaining in timeslice
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static int s_lastCycles;
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/******************************************************************************
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68K Interface
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******************************************************************************/
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// CPU state
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UINT32 M68KGetARegister(int n)
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{
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m68k_register_t r;
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switch (n)
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{
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case 0: r = M68K_REG_A0; break;
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case 1: r = M68K_REG_A1; break;
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case 2: r = M68K_REG_A2; break;
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case 3: r = M68K_REG_A3; break;
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case 4: r = M68K_REG_A4; break;
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case 5: r = M68K_REG_A5; break;
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case 6: r = M68K_REG_A6; break;
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case 7: r = M68K_REG_A7; break;
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default: r = M68K_REG_A7; break;
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}
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return m68k_get_reg(NULL, r);
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}
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UINT32 M68KGetDRegister(int n)
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{
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m68k_register_t r;
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switch (n)
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{
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case 0: r = M68K_REG_D0; break;
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case 1: r = M68K_REG_D1; break;
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case 2: r = M68K_REG_D2; break;
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case 3: r = M68K_REG_D3; break;
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case 4: r = M68K_REG_D4; break;
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case 5: r = M68K_REG_D5; break;
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case 6: r = M68K_REG_D6; break;
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case 7: r = M68K_REG_D7; break;
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default: r = M68K_REG_D7; break;
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}
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return m68k_get_reg(NULL, r);
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}
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UINT32 M68KGetPC(void)
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{
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return m68k_get_reg(NULL, M68K_REG_PC);
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}
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void M68KSaveState(CBlockFile *StateFile, const char *name)
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{
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StateFile->NewBlock(name, __FILE__);
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/*
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* Rather than writing the context directly, the get/set register
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* functions are used, ensuring that all context members are packed/
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* unpacked correctly.
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*
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* Note: Some of these are undoubtedly 68010 or 68020 registers and not
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* really necessary. But if the layout is changed now, the save state
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* version has to be changed, so don't do it!
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*/
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UINT32 data[34];
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m68ki_cpu_core Ctx;
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m68k_get_context(&Ctx);
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data[0] = Ctx.int_level;
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data[1] = Ctx.int_cycles;
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data[2] = Ctx.stopped;
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data[3] = m68k_get_reg(NULL, M68K_REG_D0);
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data[4] = m68k_get_reg(NULL, M68K_REG_D1);
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data[5] = m68k_get_reg(NULL, M68K_REG_D2);
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data[6] = m68k_get_reg(NULL, M68K_REG_D3);
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data[7] = m68k_get_reg(NULL, M68K_REG_D4);
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data[8] = m68k_get_reg(NULL, M68K_REG_D5);
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data[9] = m68k_get_reg(NULL, M68K_REG_D6);
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data[10] = m68k_get_reg(NULL, M68K_REG_D7);
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data[11] = m68k_get_reg(NULL, M68K_REG_A0);
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data[12] = m68k_get_reg(NULL, M68K_REG_A1);
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data[13] = m68k_get_reg(NULL, M68K_REG_A2);
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data[14] = m68k_get_reg(NULL, M68K_REG_A3);
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data[15] = m68k_get_reg(NULL, M68K_REG_A4);
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data[16] = m68k_get_reg(NULL, M68K_REG_A5);
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data[17] = m68k_get_reg(NULL, M68K_REG_A6);
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data[18] = m68k_get_reg(NULL, M68K_REG_A7);
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data[19] = m68k_get_reg(NULL, M68K_REG_PC);
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data[20] = m68k_get_reg(NULL, M68K_REG_SR);
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data[21] = m68k_get_reg(NULL, M68K_REG_SP);
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data[22] = m68k_get_reg(NULL, M68K_REG_USP);
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data[23] = m68k_get_reg(NULL, M68K_REG_ISP);
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data[24] = m68k_get_reg(NULL, M68K_REG_MSP);
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data[25] = m68k_get_reg(NULL, M68K_REG_SFC);
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data[26] = m68k_get_reg(NULL, M68K_REG_DFC);
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data[27] = m68k_get_reg(NULL, M68K_REG_VBR);
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data[28] = m68k_get_reg(NULL, M68K_REG_CACR);
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data[29] = m68k_get_reg(NULL, M68K_REG_CAAR);
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data[30] = m68k_get_reg(NULL, M68K_REG_PREF_ADDR);
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data[31] = m68k_get_reg(NULL, M68K_REG_PREF_DATA);
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data[32] = m68k_get_reg(NULL, M68K_REG_PPC);
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data[33] = m68k_get_reg(NULL, M68K_REG_IR);
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StateFile->Write(data, sizeof(data));
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}
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void M68KLoadState(CBlockFile *StateFile, const char *name)
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{
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if (OKAY != StateFile->FindBlock(name))
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{
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ErrorLog("Unable to load 68K state. Save state file is corrupt.");
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return;
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}
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UINT32 data[34];
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m68ki_cpu_core Ctx;
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StateFile->Read(data, sizeof(data));
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// These must be set first, to ensure another contexts' IRQs aren't active when PC is changed
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m68k_get_context(&Ctx);
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Ctx.int_level = data[0];
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Ctx.int_cycles = data[1];
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Ctx.stopped = data[2];
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m68k_set_context(&Ctx); // write them back to context
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m68k_set_reg(M68K_REG_D0, data[3]);
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m68k_set_reg(M68K_REG_D1, data[4]);
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m68k_set_reg(M68K_REG_D2, data[5]);
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m68k_set_reg(M68K_REG_D3, data[6]);
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m68k_set_reg(M68K_REG_D4, data[7]);
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m68k_set_reg(M68K_REG_D5, data[8]);
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m68k_set_reg(M68K_REG_D6, data[9]);
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m68k_set_reg(M68K_REG_D7, data[10]);
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m68k_set_reg(M68K_REG_A0, data[11]);
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m68k_set_reg(M68K_REG_A1, data[12]);
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m68k_set_reg(M68K_REG_A2, data[13]);
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m68k_set_reg(M68K_REG_A3, data[14]);
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m68k_set_reg(M68K_REG_A4, data[15]);
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m68k_set_reg(M68K_REG_A5, data[16]);
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m68k_set_reg(M68K_REG_A6, data[17]);
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m68k_set_reg(M68K_REG_A7, data[18]);
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m68k_set_reg(M68K_REG_PC, data[19]);
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m68k_set_reg(M68K_REG_SR, data[20]);
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m68k_set_reg(M68K_REG_SP, data[21]);
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m68k_set_reg(M68K_REG_USP, data[22]);
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m68k_set_reg(M68K_REG_ISP, data[23]);
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m68k_set_reg(M68K_REG_MSP, data[24]);
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m68k_set_reg(M68K_REG_SFC, data[25]);
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m68k_set_reg(M68K_REG_DFC, data[26]);
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m68k_set_reg(M68K_REG_VBR, data[27]);
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m68k_set_reg(M68K_REG_CACR, data[28]);
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m68k_set_reg(M68K_REG_CAAR, data[29]);
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m68k_set_reg(M68K_REG_PREF_ADDR, data[30]);
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m68k_set_reg(M68K_REG_PREF_DATA, data[31]);
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m68k_set_reg(M68K_REG_PPC, data[32]);
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m68k_set_reg(M68K_REG_IR, data[33]);
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}
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// Emulation functions
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void M68KSetIRQ(int irqLevel)
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{
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m68k_set_irq(irqLevel);
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}
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int M68KRun(int numCycles)
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{
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#ifdef SUPERMODEL_DEBUGGER
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if (s_Debug != NULL)
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{
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s_Debug->CPUActive();
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s_lastCycles += numCycles;
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}
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#endif // SUPERMODEL_DEBUGGER
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int doneCycles = m68k_execute(numCycles);
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#ifdef SUPERMODEL_DEBUGGER
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if (s_Debug != NULL)
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{
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s_Debug->CPUInactive();
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s_lastCycles -= m68k_cycles_remaining();
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}
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#endif // SUPERMODEL_DEBUGGER
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return doneCycles;
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}
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void M68KReset(void)
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{
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m68k_pulse_reset();
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#ifdef SUPERMODEL_DEBUGGER
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s_lastCycles = 0;
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#endif
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DebugLog("68K reset\n");
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}
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// Callback setup
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void M68KSetIRQCallback(int (*F)(int nIRQ))
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{
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IRQAck = F;
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}
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void M68KAttachBus(IBus *BusPtr)
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{
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s_Bus = BusPtr;
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DebugLog("Attached bus to 68K\n");
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}
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// Context switching
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void M68KGetContext(M68KCtx *Dest)
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{
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Dest->IRQAck = IRQAck;
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Dest->Bus = s_Bus;
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#ifdef SUPERMODEL_DEBUGGER
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Dest->Debug = s_Debug;
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#endif // SUPERMODEL_DEBUGGER
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m68k_get_context(&(Dest->musashiCtx));
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}
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void M68KSetContext(M68KCtx *Src)
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{
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IRQAck = Src->IRQAck;
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s_Bus = Src->Bus;
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#ifdef SUPERMODEL_DEBUGGER
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s_Debug = Src->Debug;
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#endif // SUPERMODEL_DEBUGGER
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m68k_set_context(&(Src->musashiCtx));
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}
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// One-time initialization
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bool M68KInit(void)
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{
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m68k_init();
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m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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m68k_set_int_ack_callback(M68KIRQCallback);
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s_Bus = NULL;
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#ifdef SUPERMODEL_DEBUGGER
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s_Debug = NULL;
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#endif // SUPERMODEL_DEBUGGER
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DebugLog("Initialized 68K\n");
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return OKAY;
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}
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#ifdef SUPERMODEL_DEBUGGER
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UINT32 M68KGetRegister(M68KCtx *Src, unsigned reg)
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{
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switch (reg)
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{
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case DBG68K_REG_PC: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_PC);
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case DBG68K_REG_SR: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_SR);
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case DBG68K_REG_SP: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_SP);
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case DBG68K_REG_D0: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D0);
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case DBG68K_REG_D1: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D1);
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case DBG68K_REG_D2: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D2);
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case DBG68K_REG_D3: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D3);
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case DBG68K_REG_D4: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D4);
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case DBG68K_REG_D5: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D5);
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case DBG68K_REG_D6: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D6);
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case DBG68K_REG_D7: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_D7);
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case DBG68K_REG_A0: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A0);
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case DBG68K_REG_A1: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A1);
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case DBG68K_REG_A2: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A2);
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case DBG68K_REG_A3: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A3);
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case DBG68K_REG_A4: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A4);
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case DBG68K_REG_A5: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A5);
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case DBG68K_REG_A6: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A6);
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case DBG68K_REG_A7: return m68k_get_reg(&(Src->musashiCtx), M68K_REG_A7);
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default: return 0;
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}
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}
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UINT32 M68KSetRegister(M68KCtx *Src, unsigned reg, UINT32 val)
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{
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switch (reg)
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{
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case DBG68K_REG_PC: m68k_set_reg(M68K_REG_PC, val); return true;
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case DBG68K_REG_SR: m68k_set_reg(M68K_REG_SR, val); return true;
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case DBG68K_REG_SP: m68k_set_reg(M68K_REG_SP, val); return true;
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case DBG68K_REG_D0: m68k_set_reg(M68K_REG_D0, val); return true;
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case DBG68K_REG_D1: m68k_set_reg(M68K_REG_D1, val); return true;
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case DBG68K_REG_D2: m68k_set_reg(M68K_REG_D2, val); return true;
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case DBG68K_REG_D3: m68k_set_reg(M68K_REG_D3, val); return true;
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case DBG68K_REG_D4: m68k_set_reg(M68K_REG_D4, val); return true;
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case DBG68K_REG_D5: m68k_set_reg(M68K_REG_D5, val); return true;
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case DBG68K_REG_D6: m68k_set_reg(M68K_REG_D6, val); return true;
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case DBG68K_REG_D7: m68k_set_reg(M68K_REG_D7, val); return true;
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case DBG68K_REG_A0: m68k_set_reg(M68K_REG_A0, val); return true;
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case DBG68K_REG_A1: m68k_set_reg(M68K_REG_A1, val); return true;
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case DBG68K_REG_A2: m68k_set_reg(M68K_REG_A2, val); return true;
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case DBG68K_REG_A3: m68k_set_reg(M68K_REG_A3, val); return true;
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case DBG68K_REG_A4: m68k_set_reg(M68K_REG_A4, val); return true;
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case DBG68K_REG_A5: m68k_set_reg(M68K_REG_A5, val); return true;
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case DBG68K_REG_A6: m68k_set_reg(M68K_REG_A6, val); return true;
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case DBG68K_REG_A7: m68k_set_reg(M68K_REG_A7, val); return true;
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default: return false;
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}
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}
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#endif // SUPERMODEL_DEBUGGER
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/******************************************************************************
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Musashi 68K Handlers
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Musashi/m68kconf.h has been configured to call these directly.
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******************************************************************************/
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extern "C" {
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#ifdef SUPERMODEL_DEBUGGER
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void M68KDebugCallback()
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{
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if (s_Debug != NULL)
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{
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UINT32 pc = m68k_get_reg(NULL, M68K_REG_PC);
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UINT32 opcode = s_Bus->Read16(pc);
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s_Debug->CPUExecute(pc, opcode, s_lastCycles - m68k_cycles_remaining());
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s_lastCycles = m68k_cycles_remaining();
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}
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}
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#endif // SUPERMODEL_DEBUGGER
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int M68KIRQCallback(int nIRQ)
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{
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#ifdef SUPERMODEL_DEBUGGER
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if (s_Debug != NULL)
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{
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s_Debug->CPUException(25);
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s_Debug->CPUInterrupt(nIRQ - 1);
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}
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#endif // SUPERMODEL_DEBUGGER
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if (NULL == IRQAck) // no handler, use default behavior
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{
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m68k_set_irq(0); // clear line
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return M68K_IRQ_AUTOVECTOR;
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}
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else
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return IRQAck(nIRQ);
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}
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unsigned int FASTCALL M68KFetch8(unsigned int a)
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{
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return s_Bus->Read8(a);
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}
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unsigned int FASTCALL M68KFetch16(unsigned int a)
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{
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return s_Bus->Read16(a);
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}
|
|
|
|
unsigned int FASTCALL M68KFetch32(unsigned int a)
|
|
{
|
|
return s_Bus->Read32(a);
|
|
}
|
|
|
|
unsigned int FASTCALL M68KRead8(unsigned int a)
|
|
{
|
|
return s_Bus->Read8(a);
|
|
}
|
|
|
|
unsigned int FASTCALL M68KRead16(unsigned int a)
|
|
{
|
|
return s_Bus->Read16(a);
|
|
}
|
|
|
|
unsigned int FASTCALL M68KRead32(unsigned int a)
|
|
{
|
|
return s_Bus->Read32(a);
|
|
}
|
|
|
|
void FASTCALL M68KWrite8(unsigned int a, unsigned int d)
|
|
{
|
|
s_Bus->Write8(a, d);
|
|
}
|
|
|
|
void FASTCALL M68KWrite16(unsigned int a, unsigned int d)
|
|
{
|
|
s_Bus->Write16(a, d);
|
|
}
|
|
|
|
void FASTCALL M68KWrite32(unsigned int a, unsigned int d)
|
|
{
|
|
s_Bus->Write32(a, d);
|
|
}
|
|
|
|
} // extern "C"
|