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510 lines
16 KiB
C++
510 lines
16 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* Real3D.h
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*
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* Header file defining the CReal3D class: the Model 3's Real3D-based graphics
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* hardware.
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*/
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#ifndef INCLUDED_REAL3D_H
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#define INCLUDED_REAL3D_H
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#include "IRQ.h"
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#include "PCI.h"
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#include "CPU/Bus.h"
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#include "Graphics/IRender3D.h"
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#include "Util/NewConfig.h"
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#include <cstdint>
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#include <unordered_map>
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/*
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* QueuedUploadTextures:
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*
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* When rendering is multi-threaded, this struct is used to represent a postponed
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* call to CRender3D::UploadTextures that will be performed by the render thread
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* at the beginning of the next frame, rather than directly in the PPC thread.
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*/
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struct QueuedUploadTextures
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{
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unsigned level; // mipmap level of the texture, saves calculating this later
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unsigned x;
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unsigned y;
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unsigned width;
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unsigned height;
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};
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/*
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* CReal3D:
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*
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* Model 3 Real3D-based graphics hardware. This class manages the hardware
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* state and drives the rendering process (scene database traversal). Actual
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* rasterization and matrix transformations are carried out by the graphics
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* engine.
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*/
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class CReal3D: public IPCIDevice
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{
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public:
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/*
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* PCI IDs
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*
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* The CReal3D object must be configured with the PCI ID of the ASIC directly
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* connected to the PCI slot; 0x16c311db for Step 1.x, 0x178611db for Step
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* 2.x. Requesting PCI ID via the DMA device on Step 2.x appears to return
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* the PCI ID of Mercury which is the ASIC connected to the PCI slot on Step
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* 1.x, hence why some Step 2.x games appear to expect the 1.x ID.
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*
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* The vendor ID code 0x11db is Sega's.
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*/
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enum PCIID: uint32_t
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{
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Step1x = 0x16C311DB, // Step 1.x
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Step2x = 0x178611DB // Step 2.x
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};
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/*
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* ASIC Names
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*
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* These were determined from Virtual On, which prints them out if any of the
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* ID codes are incorrect. ID codes depend on stepping.
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*/
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enum ASIC
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{
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Mercury,
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Venus,
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Earth,
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Mars,
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Jupiter
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};
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/*
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* SaveState(SaveState):
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*
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* Saves an image of the current device state.
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*
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* Parameters:
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* SaveState Block file to save state information to.
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*/
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void SaveState(CBlockFile *SaveState);
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/*
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* LoadState(SaveState):
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*
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* Loads and a state image.
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*
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* Parameters:
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* SaveState Block file to load state information from.
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*/
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void LoadState(CBlockFile *SaveState);
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/*
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* BeginVBlank(void):
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*
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* Must be called before the VBlank starts.
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*/
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void BeginVBlank(int statusCycles);
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/*
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* EndVBlank(void)
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*
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* Must be called after the VBlank finishes.
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*/
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void EndVBlank(void);
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/*
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* SyncSnapshots(void):
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*
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* Syncs the read-only memory snapshots with the real ones so that rendering
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* of the current frame can begin in the render thread. Must be called at the
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* end of each frame when both the render thread and the PPC thread have finished
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* their work. If multi-threaded rendering is not enabled, then this method does
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* nothing.
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*/
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uint32_t SyncSnapshots(void);
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/*
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* BeginFrame(void):
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*
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* Prepares to render a new frame. Must be called once per frame prior to
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* drawing anything and must only access read-only snapshots and variables
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* since it may be running in a separate thread.
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*/
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void BeginFrame(void);
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/*
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* RenderFrame(void):
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*
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* Traverses the scene database and renders a frame. Must be called after
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* BeginFrame() but before EndFrame() and must only access read-only snapshots
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* and variables since it may be running in a separate thread.
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*/
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void RenderFrame(void);
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/*
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* EndFrame(void):
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*
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* Signals the end of rendering for this frame. Must be called last during
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* the frame and must only access read-only snapshots and variables since it
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* may be running in a separate thread.
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*/
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void EndFrame(void);
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/*
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* Flush(void):
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*
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* Triggers the beginning of a new frame. All textures in the texture FIFO
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* are uploaded and the FIFO is reset. On the real device, this seems to
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* cause a frame to be rendered as well but this is not performed here.
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*
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* This should be called when the command port is written.
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*/
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void Flush(void);
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/*
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* ReadDMARegister8(reg):
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* ReadDMARegister32(reg):
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*
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* Reads from a DMA register. Multi-byte reads are returned as little
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* endian and must be flipped if called by a big endian device.
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*
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* Parameters:
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* reg Register number to read from (0-0xFF only).
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*
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* Returns:
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* Data of the requested size, in little endian.
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*/
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uint8_t ReadDMARegister8(unsigned reg);
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uint32_t ReadDMARegister32(unsigned reg);
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/*
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* WriteDMARegister8(reg, data):
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* WriteDMARegister32(reg, data);
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*
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* Write to a DMA register. Multi-byte writes by big endian devices must be
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* byte reversed (this is a little endian device).
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*
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* Parameters:
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* reg Register number to read from (0-0xFF only).
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* data Data to write.
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*/
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void WriteDMARegister8(unsigned reg, uint8_t data);
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void WriteDMARegister32(unsigned reg, uint32_t data);
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/*
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* WriteLowCullingRAM(addr, data):
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*
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* Writes the low culling RAM region. Because this is a little endian
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* device, big endian devices/buses have to take care to manually reverse
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* the data before writing.
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*
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* Parameters:
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* addr Word (32-bit) aligned address ranging from 0 to 0x3FFFFC.
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* User must ensure address is properly clamped.
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* data Data to write.
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*/
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void WriteLowCullingRAM(uint32_t addr, uint32_t data);
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/*
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* WriteHighCullingRAM(addr, data):
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*
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* Writes the high culling RAM region. Because this is a little endian
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* device, big endian devices/buses have to take care to manually reverse
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* the data before writing.
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*
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* Parameters:
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* addr Word (32-bit) aligned address ranging from 0 to 0xFFFFC.
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* User must ensure address is properly clamped.
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* data Data to write.
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*/
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void WriteHighCullingRAM(uint32_t addr, uint32_t data);
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/*
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* WriteTextureFIFO(data):
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*
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* Writes to the 1MB texture FIFO. Because this is a little endian device,
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* big endian devices/buses have to take care to manually reverse the data
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* before writing.
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*
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* Parameters:
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* data Data to write.
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*/
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void WriteTextureFIFO(uint32_t data);
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/*
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* WriteTexturePort(reg, data):
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*
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* Writes to the VROM texture ports. Register 0 is the word-granular VROM
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* address of the texture, register 4 is the texture information header,
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* and register 8 is the size of the texture in words.
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*
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* Parameters:
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* reg Register number: must be 0, 4, 8, 0xC, 0x10, or 0x14 only.
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* data The 32-bit word to write to the register. A write to
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* register 8 triggers the upload.
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*/
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void WriteTexturePort(unsigned reg, uint32_t data);
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/*
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* WritePolygonRAM(addr, data):
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*
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* Writes the polygon RAM region. Because this is a little endian device,
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* big endian devices/buses have to take care to manually reverse the data
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* before writing.
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*
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* Parameters:
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* addr Word (32-bit) aligned address ranging from 0 to 0x3FFFFC.
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* User must ensure address is properly clamped.
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* data Data to write.
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*/
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void WritePolygonRAM(uint32_t addr, uint32_t data);
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/*
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* WriteJTAGRegister(instruction, data):
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*
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* Write to an internal register using the JTAG interface. This is intended
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* to be called from the JTAG emulation for instructions that are known to
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* poke the internal state of Real3D ASICs.
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*
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* Parameters:
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* instruction Value of the JTAG instruction register.
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* data Data written.
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*/
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void WriteJTAGRegister(uint64_t instruction, uint64_t data);
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/*
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* ReadRegister(reg):
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*
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* Reads one of the status registers.
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*
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* Parameters:
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* reg Register offset (32-bit aligned). From 0x00 to 0x3C.
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*
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* Returns:
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* The 32-bit status register.
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*/
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uint32_t ReadRegister(unsigned reg);
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/*
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* ReadPCIConfigSpace(device, reg, bits, offset):
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*
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* Reads a PCI configuration space register. See CPCIDevice definition for
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* more details.
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*
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* Parameters:
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* device Device number (ignored, not needed).
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* reg Register number.
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* bits Bit width of access (8, 16, or 32 only).;
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* offset Byte offset within register, aligned to the specified bit
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* width, and offset from the 32-bit aligned base of the
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* register number.
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*
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* Returns:
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* Register data.
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*/
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uint32_t ReadPCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned width);
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/*
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* WritePCIConfigSpace(device, reg, bits, offset, data):
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*
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* Writes to a PCI configuration space register. See CPCIDevice definition
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* for more details.
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*
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* Parameters:
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* device Device number (ignored, not needed).
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* reg Register number.
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* bits Bit width of access (8, 16, or 32 only).
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* offset Byte offset within register, aligned to the specified bit
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* width, and offset from the 32-bit aligned base of the
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* register number.
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* data Data.
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*/
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void WritePCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned width, uint32_t data);
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/*
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* Reset(void):
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*
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* Resets the Real3D device. Must be called before reading/writing the
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* device.
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*/
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void Reset(void);
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/*
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* AttachRenderer(render3DPtr):
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*
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* Attaches a 3D renderer for the Real3D to use. This function will
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* immediately pass along the information that a CRender3D object needs to
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* work with.
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*
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* Parameters:
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* Render3DPtr Pointer to a 3D renderer object.
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*/
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void AttachRenderer(IRender3D *Render3DPtr);
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/*
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* GetASICIDCodes(asic):
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*
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* Obtain ASIC ID code for the specified ASIC under the currently configured
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* hardware stepping.
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*
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* Parameters:
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* asic ASIC ID.
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*
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* Returns:
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* The ASIC ID code. Undefined for invalid ASIC ID.
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*/
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uint32_t GetASICIDCode(ASIC asic) const;
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/*
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* SetStepping(stepping):
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*
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* Sets the Model 3 hardware stepping, which also determines the Real3D
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* functionality. The default is Step 1.0. This should be called prior to
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* any other emulation functions and after Init().
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*
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* Parameters:
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* stepping 0x10 for Step 1.0, 0x15 for Step 1.5, 0x20 for Step 2.0, or
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* 0x21 for Step 2.1. Anything else defaults to 1.0.
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*/
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void SetStepping(int stepping);
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/*
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* Init(vromPtr, BusObjectPtr, IRQObjectPtr, dmaIRQBit):
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*
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* One-time initialization of the context. Must be called prior to all
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* other members. Connects the Real3D device to its video ROM and allocates
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* memory for RAM regions.
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*
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* Parameters:
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* vromPtr A pointer to video ROM (with each 32-bit word in
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* its native little endian format).
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* BusObjectPtr Pointer to the bus that the 53C810 has control
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* over. Used to read/write memory.
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* IRQObjectPtr Pointer to the IRQ controller. Used to trigger SCSI
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* and DMA interrupts.
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* dmaIRQBit IRQ identifier bit to pass along to IRQ controller
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* when asserting interrupts.
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*
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* Returns:
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* OKAY if successful otherwise FAIL (not enough memory). Prints own
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* errors.
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*/
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bool Init(const uint8_t *vromPtr, IBus *BusObjectPtr, CIRQ *IRQObjectPtr, unsigned dmaIRQBit);
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/*
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* CReal3D(config):
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* ~CReal3D(void):
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*
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* Constructor and destructor.
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*
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* Paramters:
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* config Run-time configuration. The reference should be held because
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* this changes at run-time.
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*/
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CReal3D(const Util::Config::Node &config);
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~CReal3D(void);
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private:
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// Private member functions
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void DMACopy(void);
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void StoreTexture(unsigned level, unsigned xPos, unsigned yPos, unsigned width, unsigned height, const uint16_t *texData, bool sixteenBit, bool writeLSB, bool writeMSB, uint32_t &texDataOffset);
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void UploadTexture(uint32_t header, const uint16_t *texData);
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uint32_t UpdateSnapshots(bool copyWhole);
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uint32_t UpdateSnapshot(bool copyWhole, uint8_t *src, uint8_t *dst, unsigned size, uint8_t *dirty);
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// Config
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const Util::Config::Node &m_config;
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const bool m_gpuMultiThreaded;
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// Renderer attached to the Real3D
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IRender3D *Render3D;
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// Data passed from Model 3 object
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const uint32_t *vrom; // Video ROM
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int step; // hardware stepping (as in GameInfo structure)
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uint32_t pciID; // PCI vendor and device ID
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// Error flag (to limit errors to once per frame)
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bool error; // true if an error occurred this frame
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// Real3D memory
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uint8_t *memoryPool; // all memory allocated here
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uint32_t *cullingRAMLo; // 4MB of culling RAM at 8C000000
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uint32_t *cullingRAMHi; // 1MB of culling RAM at 8E000000
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uint32_t *polyRAM; // 4MB of polygon RAM at 98000000
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uint16_t *textureRAM; // 8MB of internal texture RAM
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uint32_t *textureFIFO; // 1MB texture FIFO at 0x94000000
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uint32_t fifoIdx; // index into texture FIFO
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uint32_t m_vromTextureFIFO[2];
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uint32_t m_vromTextureFIFOIdx;
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// Read-only snapshots
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uint32_t *cullingRAMLoRO; // 4MB of culling RAM at 8C000000 [read-only snapshot]
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uint32_t *cullingRAMHiRO; // 1MB of culling RAM at 8E000000 [read-only snapshot]
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uint32_t *polyRAMRO; // 4MB of polygon RAM at 98000000 [read-only snapshot]
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uint16_t *textureRAMRO; // 8MB of internal texture RAM [read-only snapshot]
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// Arrays to keep track of dirty pages in memory regions
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uint8_t *cullingRAMLoDirty;
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uint8_t *cullingRAMHiDirty;
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uint8_t *polyRAMDirty;
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uint8_t *textureRAMDirty;
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// Queued texture uploads
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std::vector<QueuedUploadTextures> queuedUploadTextures;
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std::vector<QueuedUploadTextures> queuedUploadTexturesRO; // Read-only copy of queue
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// Big endian bus object for DMA memory access
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IBus *Bus;
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// IRQ handling
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CIRQ *IRQ; // IRQ controller
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uint32_t dmaIRQ; // IRQ bit to use when calling IRQ handler
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// DMA device
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uint32_t dmaSrc;
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uint32_t dmaDest;
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uint32_t dmaLength;
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uint32_t dmaData;
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uint32_t dmaUnknownReg;
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uint8_t dmaStatus;
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uint8_t dmaConfig;
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// Command port
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bool commandPortWritten;
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bool commandPortWrittenRO; // Read-only copy of flag
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// Status and command registers
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uint32_t m_pingPong;
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uint64_t statusChange = 0;
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bool m_evenFrame = false;
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// Internal ASIC state
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std::unordered_map<ASIC, uint32_t> m_asicID;
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uint64_t m_internalRenderConfig[2];
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};
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#endif // INCLUDED_REAL3D_H
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