mirror of
https://github.com/RetroDECK/Supermodel.git
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151 lines
3.5 KiB
C++
151 lines
3.5 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* IRQ.h
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*
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* Header file defining the CIRQ class: Model 3 IRQ controller.
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*/
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#ifndef INCLUDED_IRQ_H
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#define INCLUDED_IRQ_H
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#include "BlockFile.h"
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#include "Types.h"
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/*
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* CIRQ:
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*
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* Model 3 IRQ controller.
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*/
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class CIRQ
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{
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public:
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/*
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* SaveState(SaveState):
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*
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* Saves an image of the current device state.
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*
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* Parameters:
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* SaveState Block file to save state information to.
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*/
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void SaveState(CBlockFile *SaveState);
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/*
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* LoadState(SaveState):
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*
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* Loads and a state image.
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*
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* Parameters:
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* SaveState Block file to load state information from.
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*/
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void LoadState(CBlockFile *SaveState);
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/*
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* Assert(irqBits):
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*
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* Assert IRQ(s). Also asserts the CPU IRQ line (unless no IRQs are
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* actually asserted). The IRQ controller only tracks 8 state bits but for
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* non-maskable interrupts, higher bits (bits 9 and above) can be used.
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* They will be tracked internally but not visible when external hardware
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* tries reading the IRQ state.
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*
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* Parameters:
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* irqBits IRQ bits corresponding to the IRQ state register (1
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* indicates assertion, 0 does nothing).
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*/
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void Assert(unsigned irqBits);
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/*
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* Deassert(irqBits):
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*
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* Deasserts the specified IRQs and, if there are no pending IRQs left,
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* deasserts the CPU IRQ line.
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*
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* Parameters:
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* irqBits IRQ bits corresponding to the IRQ state register (1
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* indicates deassertion, 0 does nothing).
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*/
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void Deassert(unsigned irqBits);
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/*
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* ReadIRQEnable(void):
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*
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* Returns:
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* The 8-bit IRQ enable register.
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*/
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UINT8 ReadIRQEnable(void);
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/*
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* WriteIRQEnable(data):
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*
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* Write to the IRQ enable register. A 1 indicates the IRQ is enabled. Only
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* the first 8 IRQs can be masked.
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*
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* Parameters:
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* data IRQ enable bits (8 bits).
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*/
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void WriteIRQEnable(UINT8 data);
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/*
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* ReadIRQState(void):
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*
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* Accesses the IRQ state register. Set bits indicate pending IRQs. Only
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* the low 8 bits are returned. Any IRQs occupying bits above this are
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* effectively invisible and non-maskable.
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*
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* Returns:
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* The 8-bit IRQ state register.
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*/
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UINT8 ReadIRQState(void);
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/*
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* Reset(void):
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*
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* Resets the IRQ controller. All IRQs are disabled.
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*/
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void Reset(void);
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/*
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* Init(void):
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*
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* One-time initialization of the context. Must be called prior to all
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* other members.
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*/
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void Init(void);
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/*
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* CIRQ(void):
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* ~CIRQ(void):
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*
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* Constructor and destructor.
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*/
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CIRQ(void);
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~CIRQ(void);
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private:
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unsigned irqEnable; // 8 bits, 1=enabled, 0=disabled
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unsigned irqState; // bits correspond to irqEnable, 1=pending, 0=not pending
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};
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#endif // INCLUDED_IRQ_H
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