mirror of
https://github.com/RetroDECK/Supermodel.git
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368 lines
9.7 KiB
C
368 lines
9.7 KiB
C
/*
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* Sega Model 3 Emulator
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* Copyright (C) 2003 Bart Trzynadlowski, Ville Linde, Stefano Teso
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License Version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program (license.txt); if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* scsi.c
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*
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* NCR 53C810 SCSI controller emulation.
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*
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* Multi-byte data written is assumed to be little endian and is therefore
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* reversed because the PowerPC operates in big endian mode in the Model 3.
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*
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* NOTE: scsi_run() is often called with an argument of 100. This is
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* actually incorrect. It should run until an interrupt condition. A count of
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* 100 is used as a runaway counter to prevent lock-ups.
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*/
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#include "model3.h"
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/*
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* Read/Write Handlers
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*
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* These are used as an interface to the rest of the system.
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*/
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static UINT8 (*read_8)(UINT32);
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static UINT16 (*read_16)(UINT32);
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static UINT32 (*read_32)(UINT32);
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static void (*write_8)(UINT32, UINT8);
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static void (*write_16)(UINT32, UINT16);
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static void (*write_32)(UINT32, UINT32);
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/*
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* 53C810 Context
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*
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* Offsets within the register array correspond to register addresses but the
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* endianness in which they are stored is little endian. Macros are provided
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* to access them.
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*/
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#define REG8(r) scsi_regs[r]
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#define REG16(r) *((UINT16 *) &scsi_regs[r])
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#define REG32(r) *((UINT32 *) &scsi_regs[r])
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static UINT8 scsi_regs[0x60];
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static BOOL scripts_exec; // true if SCRIPTS code should be executed
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/*
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* SCRIPTS Emulation
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*/
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#include "scsiop.h"
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/*
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* UINT8 scsi_read_8(UINT32 addr);
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*
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* Reads from the SCSI register space.
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*
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* Parameters:
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* addr = Register address (only lower 8 bits matter.)
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*
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* Returns:
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* Returns data from the register read.
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*/
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UINT8 scsi_read_8(UINT32 addr)
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{
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UINT8 reg;
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addr &= 0xFF;
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//if (addr > 0x5F)
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// error("%08X: SCSI invalid read from %02X", ppc_get_reg(PPC_REG_PC), addr);
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reg = REG8(addr);
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switch (addr)
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{
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case 0x14:
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REG8(addr) &= 0xFE; // clear DIP
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break;
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default:
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break;
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}
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return reg;
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}
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/*
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* UINT32 scsi_read_32(UINT32 addr);
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*
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* Reads from the SCSI register space.
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*
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* Parameters:
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* addr = Register address (only lower 8 bits matter.)
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*
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* Returns:
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* Returns data from the register read.
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*/
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UINT32 scsi_read_32(UINT32 addr)
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{
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UINT32 reg;
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// error("SCSI 32-bit read from %08X", addr);
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addr &= 0xFF;
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if (addr > 0x5F)
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error("%08X: SCSI invalid read from %02X", ppc_get_pc(), addr);
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reg = REG32(addr);
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switch (addr)
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{
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case 0x14:
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error("%08X: SCSI 32-bit read from reg %02X -- don't know what to do", ppc_get_pc(), addr);
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break;
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default:
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// NOTE: some registers might have to be handled to clear certain
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// bits
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break;
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}
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return reg;
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}
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/*
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* void scsi_write_8(UINT32 addr, UINT8 data);
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*
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* Writes a byte to the SCSI register space.
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*
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* Parameters:
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* addr = Register address (only lower 8 bits matter.)
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* data = Data to write.
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*/
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void scsi_write_8(UINT32 addr, UINT8 data)
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{
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addr &= 0xFF;
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if (addr > 0x5F)
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error("%08X: SCSI invalid write8 to %02X", ppc_get_pc(), addr);
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//message(0, "%08X: SCSI %02X = %02X", ppc_get_pc(), addr, data);
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REG8(addr) = data;
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switch (addr)
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{
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case 0x3B: // DCNTL: DMA Control
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/*
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* 7 6 5 4 3 2 1 0
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* +------+------+------+------+------+------+------+------+
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* | CLSE | PFF | PFEN | SSM | IRQM | STD | IRQD | COM |
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* +------+------+------+------+------+------+------+------+
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*
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* CLSE Cache Line Size Enable
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*
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* PFF Prefetch Flush
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*
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* PFEN Prefetch Enable
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*
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* SSM Single Step Mode
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*
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* Setting this bit causes the SCSI to stop after executing
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* each SCRIPTS instruction and generate a single step
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* interrupt. To restart the SCSI after the interrupt has
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* been generated, read ISTAT and DSTAT to recognize and
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* clear the interrupt, then set STD bit in this register
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* to resume execution.
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*
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* IRQM IRQ Mode
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*
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* STD Start DMA Operation
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*
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* The SCSI fetches an instruction and executes it when this
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* bit is set. It is required when the SCSI is in one of the
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* following modes:
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*
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* - Manual start mode: Bit 0 in the DMODE register is
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* set.
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* - Single step mode: Bit 4 in the DCNTL register is
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* set.
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*
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* When in manual mode, setting this bit starts instruction
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* execution -- it remains set until an interrupt occurs. In
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* single step mode, it restarts execution after an
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* interrupt.
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*
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* IRQD IRQ Disable
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*
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* COM LSI53C700 Family Compatibility
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*/
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/*
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* Single-stepping is checked for in scsi_run() (the number of
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* instructions to execute will be reduced to 1 there.)
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*/
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if ((REG8(0x38) & 0x01) || // MAN=1, start SCRIPTS on STD=1
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(REG8(0x3B) & 0x10)) // single step, resume execution
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{
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scripts_exec = data & 0x04;
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scsi_run(500);
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}
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break;
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}
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}
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/*
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* void scsi_write_16(UINT32 addr, UINT16 data);
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*
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* Writes a word to the SCSI register space.
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*
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* Parameters:
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* addr = Register address (only lower 8 bits matter.)
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* data = Data to write.
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*/
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void scsi_write_16(UINT32 addr, UINT16 data)
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{
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data = BSWAP16(data);
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//message(0, "%08X: SCSI %02X = %04X", ppc_get_pc(), addr, data);
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}
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/*
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* void scsi_write_32(UINT32 addr, UINT32 data);
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*
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* Writes a byte to the SCSI register space.
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*
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* Parameters:
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* addr = Register address (only lower 8 bits matter.)
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* data = Data to write.
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*/
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void scsi_write_32(UINT32 addr, UINT32 data)
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{
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if ((addr & 0xff) > 0x5C)
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error("%08X: SCSI invalid write32 to %08X", ppc_get_pc(), addr);
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addr &= 0xff;
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data = BSWAP32(data);
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REG32(addr) = data;
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// message(0, "%08X: SCSI %02X = %08X", ppc_get_reg(PPC_REG_PC), addr, data);
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switch (addr)
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{
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case 0x2C: // DSP: DMA SCRIPTS Pointer
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if ((REG8(0x38) & 0x01) == 0) // MAN=0, start SCRIPTS automatically
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scripts_exec = 1;
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scsi_run(500);
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break;
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default:
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break;
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}
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}
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/*
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* void scsi_save_state(FILE *fp);
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*
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* Saves the state of the SCSI controller to a file.
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*
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* Parameters:
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* fp = File to save to.
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*/
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void scsi_save_state(FILE *fp)
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{
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fwrite(scsi_regs, sizeof(UINT8), 0x60, fp);
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fwrite(&scripts_exec, sizeof(BOOL), 1, fp);
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}
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/*
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* void scsi_load_state(FILE *fp);
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*
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* Loads the state of the SCSI controller from a file.
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*
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* Parameters:
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* fp = File to load from.
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*/
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void scsi_load_state(FILE *fp)
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{
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fread(scsi_regs, sizeof(UINT8), 0x60, fp);
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fread(&scripts_exec, sizeof(BOOL), 1, fp);
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}
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/*
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* void scsi_reset(void);
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*
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* Initializes the SCSI controller to its power-on state. All bits which are
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* marked as undefined by the manual are simply set to 0 here.
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*/
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void scsi_reset(void)
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{
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memset(scsi_regs, 0, sizeof(scsi_regs));
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scripts_exec = 0;
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REG8(0x00) = 0xc0;
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REG8(0x0C) = 0x80;
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REG8(0x0F) = 0x02;
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REG8(0x18) = 0xff;
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REG8(0x19) = 0xf0;
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REG8(0x1A) = 0x01;
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REG8(0x46) = 0x60;
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REG8(0x47) = 0x0f;
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REG8(0x4C) = 0x03;
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}
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/*
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* void scsi_init(UINT8 (*read8)(UINT32), UINT16 (*read16)(UINT32),
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* UINT32 (*read32)(UINT32), void (*write8)(UINT32, UINT8),
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* void (*write16)(UINT32, UINT16),
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* void (*write32)(UINT32, UINT32));
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*
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* Initializes the SCSI controller emulation by building the SCRIPTS opcode
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* table and setting the memory access handlers.
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*
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* Parameters:
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* read8 = Handler to use for 8-bit reads.
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* read16 = Handler to use for 16-bit reads.
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* read32 = Handler to use for 32-bit reads.
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* write8 = Handler to use for 8-bit writes.
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* write16 = Handler to use for 16-bit writes.
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* write32 = Handler to use for 32-bit writes.
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*/
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void scsi_init(UINT8 (*read8)(UINT32), UINT16 (*read16)(UINT32),
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UINT32 (*read32)(UINT32), void (*write8)(UINT32, UINT8),
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void (*write16)(UINT32, UINT16),
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void (*write32)(UINT32, UINT32))
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{
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read_8 = read8;
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read_16 = read16;
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read_32 = read32;
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write_8 = write8;
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write_16 = write16;
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write_32 = write32;
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build_opcode_table();
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}
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/*
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* void scsi_shutdown(void);
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*
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* Shuts down the SCSI emulation (actually does nothing.)
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*/
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void scsi_shutdown(void)
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{
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}
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