mirror of
https://github.com/RetroDECK/Supermodel.git
synced 2024-11-23 06:15:37 +00:00
03fa9532eb
- Added object interface CThread for OSD threading and synchronization, together with SDL implementation - Added multi-threading to CModel3 so that separate CPUs (PPC of main board, 68K of sound board and Z80 of drive board) can be run in separate threads if requested to improve performance on multi-core PCs - Added -multi-threaded command line option (default is to run single-threaded still)
357 lines
10 KiB
C++
357 lines
10 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* Model3.h
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*
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* Header file defining the CModel3 and CModel3Inputs classes.
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*/
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#ifndef INCLUDED_MODEL3_H
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#define INCLUDED_MODEL3_H
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/*
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* CModel3:
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*
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* A complete Model 3 system.
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*
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* Inherits CBus in order to pass the address space handlers to devices that
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* may need them (CPU, DMA, etc.)
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*
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* NOTE: Currently NOT re-entrant due to a non-OOP PowerPC core. Do NOT create
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* create more than one CModel3 object!
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*/
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class CModel3: public CBus, public CPCIDevice
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{
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public:
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/*
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* ReadPCIConfigSpace(device, reg, bits, offset):
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*
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* Handles unknown PCI devices. See CPCIDevice definition for more details.
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*
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* Parameters:
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* device Device number.
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* reg Register number.
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* bits Bit width of access (8, 16, or 32 only).;
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* offset Byte offset within register, aligned to the specified bit
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* width, and offset from the 32-bit aligned base of the
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* register number.
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*
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* Returns:
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* Register data.
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*/
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UINT32 ReadPCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned width);
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/*
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* WritePCIConfigSpace(device, reg, bits, offset, data):
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*
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* Handles unknown PCI devices. See CPCIDevice definition for more details.
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*
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* Parameters:
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* device Device number.
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* reg Register number.
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* bits Bit width of access (8, 16, or 32 only).
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* offset Byte offset within register, aligned to the specified bit
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* width, and offset from the 32-bit aligned base of the
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* register number.
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* data Data.
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*/
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void WritePCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned width, UINT32 data);
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/*
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* Read8(addr):
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* Read16(addr):
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* Read32(addr):
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* Read64(addr):
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*
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* Read a byte, 16-bit half word, 32-bit word, or 64-bit double word from
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* the PowerPC address space. This implements the PowerPC address bus. Note
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* that it is big endian, so when accessing from a little endian device,
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* the byte order must be manually reversed.
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*
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* Parameters:
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* addr Address to read.
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*
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* Returns:
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* Data at the address.
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*/
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UINT8 Read8(UINT32 addr);
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UINT16 Read16(UINT32 addr);
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UINT32 Read32(UINT32 addr);
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UINT64 Read64(UINT32 addr);
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/*
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* Write8(addr, data):
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* Write16(addr, data):
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* Write32(addr, data):
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* Write64(addr, data):
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*
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* Write a byte, half word, word, or double word to the PowerPC address
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* space. Note that everything is stored in big endian form, so when
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* accessing with a little endian device, the byte order must be manually
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* reversed.
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*
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* Parameters:
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* addr Address to write.
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* data Data to write.
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*/
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void Write8(UINT32 addr, UINT8 data);
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void Write16(UINT32 addr, UINT16 data);
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void Write32(UINT32 addr, UINT32 data);
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void Write64(UINT32 addr, UINT64 data);
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/*
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* SaveState(SaveState):
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*
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* Saves an image of the current state.
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*
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* Parameters:
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* SaveState Block file to save state information to.
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*/
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void SaveState(CBlockFile *SaveState);
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/*
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* LoadState(SaveState):
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*
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* Loads and resumes execution from a state image.
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*
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* Parameters:
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* SaveState Block file to load state information from.
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*/
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void LoadState(CBlockFile *SaveState);
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/*
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* SaveNVRAM(NVRAM):
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*
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* Saves an image of the current NVRAM state.
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*
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* Parameters:
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* NVRAM Block file to save NVRAM to.
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*/
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void SaveNVRAM(CBlockFile *NVRAM);
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/*
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* LoadNVRAM(NVRAM):
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*
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* Loads an NVRAM image.
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*
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* Parameters:
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* NVRAM Block file to load NVRAM state from.
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*/
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void LoadNVRAM(CBlockFile *NVRAM);
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/*
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* ClearNVRAM(void):
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*
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* Clears all NVRAM (backup RAM and EEPROM).
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*/
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void ClearNVRAM(void);
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/*
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* RunFrame(void):
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*
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* Runs one frame (assuming 60 Hz video refresh rate).
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*/
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void RunFrame(void);
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/*
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* Reset(void):
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*
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* Resets the system. Does not modify non-volatile memory.
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*/
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void Reset(void);
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/*
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* GetGameInfo(void):
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*
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* Returns:
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* A pointer to the presently loaded game's information structure (or
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* NULL if no ROM set has yet been loaded).
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*/
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const struct GameInfo * GetGameInfo(void);
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/*
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* LoadROMSet(GameList, zipFile):
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*
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* Loads a complete ROM set from the specified ZIP archive.
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*
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* Parameters:
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* GameList List of all supported games and their ROMs.
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* zipFile ZIP file to load from.
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*
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* Returns:
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* OKAY if successful, FAIL otherwise. Prints errors.
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*/
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BOOL LoadROMSet(const struct GameInfo *GameList, const char *zipFile);
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/*
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* AttachRenderers(Render2DPtr, Render3DPtr):
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*
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* Attaches the renderers to the appropriate device objects.
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*
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* Parameters:
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* Render2DPtr Pointer to a tile renderer object.
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* Render3DPtr Same as above but for a 3D renderer.
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*/
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void AttachRenderers(CRender2D *Render2DPtr, CRender3D *Render3DPtr);
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/*
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* AttachInputs(InputsPtr):
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*
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* Attaches OSD-managed inputs.
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*
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* Parameters:
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* InputsPtr Pointer to the object containing input states.
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*/
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void AttachInputs(CInputs *InputsPtr);
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/*
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* Init(ppcFrequencyParam, multiThreadedParam):
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*
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* One-time initialization of the context. Must be called prior to all
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* other members. Allocates memory and initializes device states.
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*
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* Parameters:
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* ppcFrequencyParam PowerPC frequency in Hz. If less than 1 MHz,
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* will be clamped to 1 MHz.
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*
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* Returns:
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* OKAY is successful, otherwise FAILED if a non-recoverable error
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* occurred. Prints own error messages.
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*/
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BOOL Init(unsigned ppcFrequencyParam, BOOL multiThreadedParam);
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/*
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* CModel3(void):
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* ~CModel3(void):
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*
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* Constructor and destructor for Model 3 class. Constructor performs a
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* bare-bones initialization of object; does not perform any memory
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* allocation or any actions that can fail. The destructor will deallocate
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* memory and free resources used by the object (and its child objects).
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*/
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CModel3(void);
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~CModel3(void);
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/*
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* Private Property.
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* Tresspassers will be shot! ;)
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*/
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private:
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// Private member functions
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UINT8 ReadInputs(unsigned reg);
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void WriteInputs(unsigned reg, UINT8 data);
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UINT32 ReadSecurity(unsigned reg);
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void WriteSecurity(unsigned reg, UINT32 data);
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void SetCROMBank(unsigned idx);
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UINT8 ReadSystemRegister(unsigned reg);
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void WriteSystemRegister(unsigned reg, UINT8 data);
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void Patch(void);
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void RunMainBoardFrame(); // Runs the main board (PPC) for a frame
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bool StartThreads(); // Starts all threads
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void StopThreads(); // Stops all threads
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void DeleteThreadObjects(); // Deletes all threads and synchronization objects
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static int StartSoundBoardThread(void *data); // Callback to start sound board thread
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#ifdef SUPERMODEL_DRIVEBOARD
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static int StartDriveBoardThread(void *data); // Callback to start drive board thread
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#endif
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void RunSoundBoardThread(); // Runs sound board thread
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#ifdef SUPERMODEL_DRIVEBOARD
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void RunDriveBoardThread(); // Runs drive board thread
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#endif
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// Game and hardware information
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const struct GameInfo *Game;
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// Game inputs
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CInputs *Inputs;
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// Input registers (game controls)
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UINT8 inputBank;
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UINT8 serialFIFO1, serialFIFO2;
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UINT8 gunReg;
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int adcChannel;
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// MIDI port
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UINT8 midiCtrlPort; // controls MIDI (SCSP) IRQ behavior
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// Emulated core Model 3 memory regions
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UINT8 *memoryPool; // single allocated region for all ROM and system RAM
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UINT8 *ram; // 8 MB PowerPC RAM
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UINT8 *crom; // 8+128 MB CROM (fixed CROM first, then 64MB of banked CROMs -- Daytona2 might need extra?)
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UINT8 *vrom; // 64 MB VROM (video ROM, visible only to Real3D)
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UINT8 *soundROM; // 512 KB sound ROM (68K program)
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UINT8 *sampleROM; // 8 MB samples (68K)
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UINT8 *backupRAM; // 128 KB Backup RAM (battery backed)
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UINT8 *securityRAM; // 128 KB Security Board RAM
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// Banked CROM
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UINT8 *cromBank; // currently mapped in CROM bank
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unsigned cromBankReg; // the CROM bank register
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// Security device
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unsigned securityPtr; // pointer to current offset in security data
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// PowerPC
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PPC_FETCH_REGION PPCFetchRegions[3];
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unsigned ppcFrequency; // clock frequency (Hz)
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// Multiple threading
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bool multiThreaded; // True if should run CPUs in multiple threads, otherwise everything is run in a single thread
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bool startedThreads; // True if threads have been created and started
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CThread *sndBrdThread; // Sound board thread
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#ifdef SUPERMODEL_DRIVEBOARD
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CThread *drvBrdThread; // Drive board thread
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#endif
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bool sndBrdThreadDone; // Flag to indicate sound board thread has finished processing for current frame
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#ifdef SUPERMODEL_DRIVEBOARD
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bool drvBrdThreadDone; // Flag to indicate drive board thread has finished processing for current frame
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#endif
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// Thread synchronization objects
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CSemaphore *sndBrdThreadSync;
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#ifdef SUPERMODEL_DRIVEBOARD
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CSemaphore *drvBrdThreadSync;
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#endif
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CMutex *notifyLock;
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CCondVar *notifySync;
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// Other devices
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CIRQ IRQ; // Model 3 IRQ controller
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CMPC10x PCIBridge; // MPC10x PCI/bridge/memory controller
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CPCIBus PCIBus; // Model 3's PCI bus
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C53C810 SCSI; // NCR 53C810 SCSI controller
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CRTC72421 RTC; // Epson RTC-72421 real-time clock
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C93C46 EEPROM; // 93C46 EEPROM
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CTileGen TileGen; // Sega 2D tile generator
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CReal3D GPU; // Real3D graphics hardware
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CSoundBoard SoundBoard; // Sound board
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#ifdef SUPERMODEL_DRIVEBOARD
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CDriveBoard DriveBoard; // Drive board
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#endif
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};
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#endif // INCLUDED_MODEL3_H
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