mirror of
https://github.com/RetroDECK/Supermodel.git
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505 lines
15 KiB
C++
505 lines
15 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* 53C810.cpp
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*
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* Implementation of the C53C810 class: NCR 53C810 SCSI controller.
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*
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* Notes:
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* ------
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* - VF3 does something weird: it writes DSP (triggering automatic code
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* execution because MAN=0) and THEN sets single step mode, expecting an
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* interrupt to occur. I suspect this is incorrect operation and that
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* the SCRIPTS processor either enters single-step mode while the memory
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* transfer is underway (though it is unlikely because it's such a short
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* transfer), or that single step can occur even when the device is "halted"
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* (which would mean the SCRIPTS processor executes an invalid instruction
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* once or twice without the VF3 SCSI driver noticing). Unfortunately, the
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* former is not feasible to emulate. If automatic SCRIPTS execution is
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* disabled when single-stepping is enabled, Scud Race breaks (glitchy,
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* jerky graphics). Enabling automatic execution and also allowing single
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* stepping to occur when the processor is halted seems to work, but it
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* causes invalid instructions to be hit each time.
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* - pg 2-22 (42) of the manual has description of how to clear interrupts.
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*
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*/
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#include "53C810.h"
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#include <cstring>
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#include "Supermodel.h"
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#include "CPU/PowerPC/ppc.h"
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/******************************************************************************
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Save States
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******************************************************************************/
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void C53C810::SaveState(CBlockFile *SaveState)
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{
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SaveState->NewBlock("53C810", __FILE__);
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SaveState->Write(Ctx.regs, sizeof(Ctx.regs));
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SaveState->Write(&Ctx.regTEMP, sizeof(Ctx.regTEMP));
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SaveState->Write(&Ctx.regDSP, sizeof(Ctx.regDSP));
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SaveState->Write(&Ctx.regDSPS, sizeof(Ctx.regDSPS));
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SaveState->Write(&Ctx.regDBC, sizeof(Ctx.regDBC));
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SaveState->Write(&Ctx.regDCMD, sizeof(Ctx.regDCMD));
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SaveState->Write(&Ctx.regDCNTL, sizeof(Ctx.regDCNTL));
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SaveState->Write(&Ctx.regDMODE, sizeof(Ctx.regDMODE));
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SaveState->Write(&Ctx.regDSTAT, sizeof(Ctx.regDSTAT));
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SaveState->Write(&Ctx.regISTAT, sizeof(Ctx.regISTAT));
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}
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void C53C810::LoadState(CBlockFile *SaveState)
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{
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if (OKAY != SaveState->FindBlock("53C810"))
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{
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ErrorLog("Unable to load 53C810 state. Save state file is corrupt.");
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return;
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}
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SaveState->Read(Ctx.regs, sizeof(Ctx.regs));
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SaveState->Read(&Ctx.regTEMP, sizeof(Ctx.regTEMP));
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SaveState->Read(&Ctx.regDSP, sizeof(Ctx.regDSP));
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SaveState->Read(&Ctx.regDSPS, sizeof(Ctx.regDSPS));
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SaveState->Read(&Ctx.regDBC, sizeof(Ctx.regDBC));
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SaveState->Read(&Ctx.regDCMD, sizeof(Ctx.regDCMD));
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SaveState->Read(&Ctx.regDCNTL, sizeof(Ctx.regDCNTL));
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SaveState->Read(&Ctx.regDMODE, sizeof(Ctx.regDMODE));
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SaveState->Read(&Ctx.regDSTAT, sizeof(Ctx.regDSTAT));
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SaveState->Read(&Ctx.regISTAT, sizeof(Ctx.regISTAT));
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}
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/******************************************************************************
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SCRIPTS Emulation
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******************************************************************************/
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static inline UINT32 Fetch(struct NCR53C810Context *Ctx, UINT32 offset)
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{
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UINT32 data = Ctx->Bus->Read32(Ctx->regDSP + offset);
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return FLIPENDIAN32(data); // remember: bus is big endian, need to convert to little endian
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}
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//TODO: what happens if interrupt is executed in single step mode?
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static bool SCRIPTS_Int_IntFly(struct NCR53C810Context *Ctx)
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{
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Ctx->halt = true; // halt SCRIPTS execution
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Ctx->regISTAT |= 1; // DMA interrupt pending
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Ctx->regDSTAT |= 4; // SCRIPTS interrupt instruction received
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Ctx->IRQ->Assert(Ctx->scsiIRQ);
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if ((Ctx->regDBC&0x100000)) // INTFLY
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return ErrorLog("53C810 INTFLY instruction not emulated!");
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// DSP not incremented (VF3 relies on this)
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return OKAY;
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}
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static bool SCRIPTS_MoveMemory(struct NCR53C810Context *Ctx)
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{
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UINT32 src, dest;
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unsigned numBytes, i;
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// Get operands
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src = Ctx->regDSPS;
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dest = Ctx->regTEMP = Fetch(Ctx, 8); // word 3
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numBytes = Ctx->regDBC;
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// Not implemented: illegal instruction interrupt when src and dest are not aligned the same way
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DebugLog("53C810: Move Memory %08X -> %08X, %X\n", src, dest, numBytes);
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//if (dest==0x94000000)printf("53C810: Move Memory %08X -> %08X, %X\n", src, dest, numBytes);
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// Perform a 32-bit copy if possible
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for (i = 0; i < (numBytes/4); i++)
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{
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Ctx->Bus->Write32(dest, Ctx->Bus->Read32(src));
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dest += 4;
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src += 4;
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}
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// Finish off the last few odd bytes
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numBytes &= 3;
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while (numBytes)
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{
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Ctx->Bus->Write8(dest++, Ctx->Bus->Read8(src++));
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--numBytes;
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}
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// Update registers
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Ctx->regDBC = 0;
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Ctx->regDSPS = src;
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Ctx->regTEMP = dest;
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Ctx->regDSP += 12;
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return OKAY;
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}
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// Invalid instruction handler
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static bool SCRIPTS_Invalid(struct NCR53C810Context *Ctx)
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{
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DebugLog("53C810 encountered an unrecognized instruction (%02X%06X, DSP=%08X)\n!", Ctx->regDCMD, Ctx->regDBC, Ctx->regDSP);
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return FAIL;
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}
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void C53C810::Run(bool singleStep)
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{
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UINT32 op;
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int i;
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if (singleStep)// && !Ctx.halt)
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{
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// Fetch instruction (first two words are always fetched)
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op = Fetch(&Ctx, 0); // word 1
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Ctx.regDBC = op&0x00FFFFFF;
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Ctx.regDCMD = (op>>24)&0xFF;
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Ctx.regDSPS = Fetch(&Ctx, 4); // word 2
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// Single step
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OpTable[Ctx.regDCMD](&Ctx);
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// Issue IRQ and finish
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Ctx.regISTAT |= 1; // DMA interrupt pending
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Ctx.regDSTAT |= 8; // single step interrupt
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Ctx.IRQ->Assert(Ctx.scsiIRQ); // generate an interrupt
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DebugLog("53C810: Asserted IRQ\n");
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}
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else
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{
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// Automatic mode: run (as long as the processor is not halted)
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for (i = 0; (i < 100) && !Ctx.halt; i++)
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{
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// Fetch instruction (first two words are always fetched)
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op = Fetch(&Ctx, 0); // word 1
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Ctx.regDBC = op&0x00FFFFFF;
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Ctx.regDCMD = (op>>24)&0xFF;
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Ctx.regDSPS = Fetch(&Ctx, 4); // word 2
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// Execute!
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if (OpTable[Ctx.regDCMD](&Ctx) != OKAY)
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break;
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}
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}
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}
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// Insert instructions into the LUT under control of the mask
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void C53C810::Insert(UINT8 mask, UINT8 op, bool (*Handler)(struct NCR53C810Context *))
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{
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UINT32 i;
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for (i = 0; i < 256; i++)
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{
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if ((i&mask) == op)
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OpTable[i] = Handler;
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}
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}
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void C53C810::BuildOpTable(void)
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{
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Insert(0, 0, &SCRIPTS_Invalid);
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Insert(0xE0, 0xC0, &SCRIPTS_MoveMemory);
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Insert(0xF8, 0x98, &SCRIPTS_Int_IntFly);
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}
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/******************************************************************************
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Register and PCI Access Handlers
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******************************************************************************/
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void C53C810::WriteRegister(unsigned reg, UINT8 data)
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{
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if (reg >= 0x60)
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{
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ErrorLog("Write to invalid 53C810 register (%02X).", reg);
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return;
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}
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DebugLog("53C810 write: %02X=%02X (PC=%08X, LR=%08X)\n", reg, data, ppc_get_pc(), ppc_get_lr());
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// Dump everything into the register file
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Ctx.regs[reg&0xFF] = data;
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// Do something extra with the ones that we actually care about
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// TO-DO: prevent invalid/reserved/read-only registers from being written?
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switch(reg)
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{
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case 0x14: // ISTAT
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Ctx.regISTAT = data;
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DebugLog("ISTAT=%02X\n", data);
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break;
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case 0x1C: // TEMP 7-0
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Ctx.regTEMP &= 0xFFFFFF00;
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Ctx.regTEMP |= data;
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break;
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case 0x1D: // TEMP 15-8
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Ctx.regTEMP &= 0xFFFF00FF;
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Ctx.regTEMP |= (data<<8);
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break;
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case 0x1E: // TEMP 23-16
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Ctx.regTEMP &= 0xFF00FFFF;
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Ctx.regTEMP |= (data<<16);
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break;
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case 0x1F: // TEMP 31-24
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Ctx.regTEMP &= 0x00FFFFFF;
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Ctx.regTEMP |= (data<<24);
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break;
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case 0x24: // DBC 7-0
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Ctx.regDBC &= 0xFFFFFF00;
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Ctx.regDBC |= data;
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break;
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case 0x25: // DBC 15-8
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Ctx.regDBC &= 0xFFFF00FF;
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Ctx.regDBC |= (data<<8);
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break;
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case 0x26: // DBC 23-16
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Ctx.regDBC &= 0xFF00FFFF;
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Ctx.regDBC |= (data<<16);
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break;
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case 0x27: // DCMD
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Ctx.regDCMD = data;
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break;
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case 0x2C: // DSP 7-0
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Ctx.regDSP &= 0xFFFFFF00;
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Ctx.regDSP |= data;
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break;
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case 0x2D: // DSP 15-8
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Ctx.regDSP &= 0xFFFF00FF;
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Ctx.regDSP |= (data<<8);
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break;
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case 0x2E: // DSP 23-16
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Ctx.regDSP &= 0xFF00FFFF;
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Ctx.regDSP |= (data<<16);
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break;
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case 0x2F: // DSP 31-24
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Ctx.regDSP &= 0x00FFFFFF;
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Ctx.regDSP |= (data<<24);
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Ctx.halt = false; // writing this register un-halts 53C810 operation (pg.6-31 of LSI manual)
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if (!(Ctx.regDMODE&1)) // if MAN=0, start SCRIPTS automatically
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// To-Do: is this correct? Should single step really be tested first?
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//if (!(Ctx.regDCNTL&0x10) && !(Ctx.regDMODE&1)) // if MAN=0 and not single stepping, start SCRIPTS automatically
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{
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DebugLog("53C810: Automatically starting (PC=%08X, LR=%08X, single step=%d)\n", ppc_get_pc(), ppc_get_lr(), !!(Ctx.regDCNTL&0x10));
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Run(false); // automatic
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}
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break;
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case 0x30: // DSPS 7-0
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Ctx.regDSPS &= 0xFFFFFF00;
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Ctx.regDSPS |= data;
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break;
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case 0x31: // DSPS 15-8
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Ctx.regDSPS &= 0xFFFF00FF;
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Ctx.regDSPS |= (data<<8);
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break;
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case 0x32: // DSPS 23-16
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Ctx.regDSPS &= 0xFF00FFFF;
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Ctx.regDSPS |= (data<<16);
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break;
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case 0x33: // DSPS 31-24
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Ctx.regDSPS &= 0x00FFFFFF;
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Ctx.regDSPS |= (data<<24);
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break;
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case 0x38: // DMODE
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Ctx.regDMODE = data;
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break;
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case 0x3B: // DCNTL
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Ctx.regDCNTL = data;
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if ((Ctx.regDCNTL&0x14) == 0x14) // single step
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{
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DebugLog("53C810: single step: %08X, (halt=%d)\n", Ctx.regDSP, Ctx.halt);
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Run(true);
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}
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else if ((Ctx.regDCNTL&0x04)) // start DMA bit
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{
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DebugLog("53C810: Manually starting\n");
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Run(false);
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}
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break;
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default:
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break;
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}
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}
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UINT8 C53C810::ReadRegister(unsigned reg)
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{
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UINT8 ret;
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if (reg >= 0x60)
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{
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ErrorLog("Read from invalid 53C810 register (%02X).", reg);
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return 0;
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}
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DebugLog("53C810 read: %02X (PC=%08X, LR=%08X)\n", reg, ppc_get_pc(), ppc_get_lr());
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// Some registers require special handling
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switch(reg)
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{
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case 0x0C: // DSTAT
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// For now, we don't generate stacked interrupts, so always clear IRQ status
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ret = Ctx.regDSTAT;
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//TO-DO: manual says these should be cleared here but MAME never clears them. What's up with that?
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Ctx.regISTAT &= 0xFE; // clear DIP bit (DMA interrupt)
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Ctx.regDSTAT &= 0xF7; // clear SSI (single step interrupt)
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//Ctx.regISTAT |= 1; // doing this is another way to fix VF3
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//Ctx.regDSTAT |= 8;
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Ctx.IRQ->Deassert(Ctx.scsiIRQ);
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//DebugLog("53C810: DSTAT read\n");
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return ret;
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case 0x14: // ISTAT
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//DebugLog("53C810: ISTAT read\n");
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return Ctx.regISTAT;
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case 0x1C: // TEMP 7-0
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return Ctx.regTEMP&0xFF;
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case 0x1D: // TEMP 15-8
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return (Ctx.regTEMP>>8)&0xFF;
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case 0x1E: // TEMP 23-16
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return (Ctx.regTEMP>>16)&0xFF;
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case 0x1F: // TEMP 31-24
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return (Ctx.regTEMP>>24)&0xFF;
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case 0x24: // DBC 7-0
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return Ctx.regDBC&0xFF;
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case 0x25: // DBC 15-8
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return (Ctx.regDBC>>8)&0xFF;
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case 0x26: // DBC 23-16
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return (Ctx.regDBC>>16)&0xFF;
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case 0x27: // DCMD
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return Ctx.regDCMD;
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case 0x2C: // DSP 7-0
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return Ctx.regDSP&0xFF;
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case 0x2D: // DSP 15-8
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return (Ctx.regDSP>>8)&0xFF;
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case 0x2E: // DSP 23-16
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return (Ctx.regDSP>>16)&0xFF;
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case 0x2F: // DSP 31-24
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return (Ctx.regDSP>>24)&0xFF;
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case 0x30: // DSPS 7-0
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return Ctx.regDSPS&0xFF;
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case 0x31: // DSPS 15-8
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return (Ctx.regDSPS>>8)&0xFF;
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case 0x32: // DSPS 23-16
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return (Ctx.regDSPS>>16)&0xFF;
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case 0x33: // DSPS 31-24
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return (Ctx.regDSPS>>24)&0xFF;
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case 0x38:
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return Ctx.regDMODE;
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case 0x3B: // DCNTL
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return Ctx.regDCNTL;
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default: // get it from the register file
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break;
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}
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// Register file should be up to date
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return Ctx.regs[reg&0xFF];
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}
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UINT32 C53C810::ReadPCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned offset)
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{
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UINT32 d;
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if ((bits==8))
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{
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DebugLog("53C810 %d-bit PCI read request for reg=%02X\n", bits, reg);
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return 0;
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}
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switch (reg)
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{
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case 0x00: // Device ID and Vendor ID
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d = FLIPENDIAN32(0x00011000); // 0x1000 = LSI Logic, 0x0001 = 53c810a
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switch (bits)
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{
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case 8:
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d >>= (3-offset)*8; // offset will be 0-3; select appropriate byte
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d &= 0xFF;
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break;
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case 16:
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d >>= (2-offset)*8; // offset will be 0 or 2 only; select either high or low word
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d &= 0xFFFF;
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break;
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default:
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break;
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}
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return d;
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default:
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DebugLog("53C810 PCI read request for reg=%02X (%d-bit)\n", reg, bits);
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break;
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}
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return 0;
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}
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void C53C810::WritePCIConfigSpace(unsigned device, unsigned reg, unsigned bits, unsigned offset, UINT32 data)
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{
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DebugLog("53C810 PCI %d-bit write request for reg=%02X, data=%08X\n", bits, reg, data);
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}
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void C53C810::Reset(void)
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{
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memset(Ctx.regs, 0, sizeof(Ctx.regs));
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Ctx.regs[0x00] = 0xC0; // SCNTL0
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Ctx.regs[0x0C] = 0x80; // DSTAT
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Ctx.regs[0x0F] = 0x02; // SSTAT2
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Ctx.regs[0x18] = 0xFF; // reserved
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Ctx.regs[0x19] = 0xF0; // CTEST1
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Ctx.regs[0x1A] = 0x01; // CTEST2
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Ctx.regs[0x46] = 0x60; // MACNTL
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Ctx.regs[0x47] = 0x0F; // GPCNTL
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Ctx.regs[0x4C] = 0x03; // STEST0
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Ctx.regTEMP = 0;
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Ctx.regDSP = 0;
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Ctx.regDSPS = 0;
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Ctx.regDBC = 0;
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Ctx.regDCMD = 0;
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Ctx.regDCNTL = 0;
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Ctx.regDMODE = 0;
|
|
Ctx.regDSTAT = 0x80; // DMA FIFO empty
|
|
Ctx.regISTAT = 0;
|
|
Ctx.halt = false;
|
|
|
|
DebugLog("53C810 reset\n");
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
Configuration, Initialization, and Shutdown
|
|
******************************************************************************/
|
|
|
|
void C53C810::Init(IBus *BusObjectPtr, CIRQ *IRQObjectPtr, unsigned scsiIRQBit)
|
|
{
|
|
Ctx.Bus = BusObjectPtr;
|
|
Ctx.IRQ = IRQObjectPtr;
|
|
Ctx.scsiIRQ = scsiIRQBit;
|
|
}
|
|
|
|
C53C810::C53C810(void)
|
|
{
|
|
BuildOpTable();
|
|
Ctx.Bus = NULL;
|
|
Ctx.IRQ = NULL;
|
|
scsiIRQ = 0;
|
|
DebugLog("Built 53C810\n");
|
|
}
|
|
|
|
C53C810::~C53C810(void)
|
|
{
|
|
Ctx.Bus = NULL;
|
|
Ctx.IRQ = NULL;
|
|
DebugLog("Destroyed 53C810\n");
|
|
}
|