mirror of
https://github.com/RetroDECK/Supermodel.git
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358 lines
11 KiB
C++
358 lines
11 KiB
C++
/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011 Bart Trzynadlowski, Nik Henson
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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/*
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* MPC10x.cpp
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*
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* Implementation of the CMPC10x class: Motorola MPC105 and MPC106 PCI/bridge
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* controllers. For now, only a single PCI bus can be attached and all requests
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* are forwarded to it.
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*
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* This is a minimal implementation designed with the Model 3 in mind. It does
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* not properly emulate the device and there are numerous inaccuracies in this
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* code.
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*
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* Important Problems To Be Aware Of
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* ---------------------------------
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*
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* The handling of accesses smaller than 32 bits is funky and probably very
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* incorrect, particularly for non-32-bit-aligned register numbers. This
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* problem extends to the entire PCI emulation.
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*
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* Little endian mode is not supported (the internal registers, however, seem
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* to be stored in little endian format). The registers are implemented as byte
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* read/writeable but this is not accurate. In fact, some are read only, and
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* some can only be accessed as 16-bit or 32-bit words.
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*
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* This code assumes we are running on a little endian machine and that the
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* PowerPC is a big endian machine. Therefore, bytes can be written to the
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* register space directly but multi-byte words must be flipped before being
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* interpreted internally.
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*
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* External configuration registers are not implemented.
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*
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* Multiple PCI buses are not yet supported (everything is assumed to be on
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* bus 0).
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*
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* ... And lots more!
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*
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* References
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* ----------
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* 1. "MPC106 PCI/Bridge/Memory Controller User's Manual" (MPC106UM/D Rev.1)
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*
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* To-Do List
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* ----------
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* - The whole PCI system desperately needs a re-write to deal with different
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* bit-width accesses in a cleaner manner.
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* - Fix endian confusion. Should assume everything written is in the correct
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* endian, pushing the responsibility onto the caller.
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*/
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#include <cstring>
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#include "Supermodel.h"
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/******************************************************************************
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Save States
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******************************************************************************/
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void CMPC10x::SaveState(CBlockFile *SaveState)
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{
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SaveState->NewBlock("MPC10x", __FILE__);
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SaveState->Write(regs, sizeof(regs));
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SaveState->Write(&pciBus, sizeof(pciBus));
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SaveState->Write(&pciDevice, sizeof(pciDevice));
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SaveState->Write(&pciFunction, sizeof(pciFunction));
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SaveState->Write(&pciReg, sizeof(pciReg));
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}
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void CMPC10x::LoadState(CBlockFile *SaveState)
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{
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if (OKAY != SaveState->FindBlock("MPC10x"))
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{
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ErrorLog("Unable to load MPC%X state. Save state file is corrupted.", model);
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return;
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}
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SaveState->Read(regs, sizeof(regs));
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SaveState->Read(&pciBus, sizeof(pciBus));
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SaveState->Read(&pciDevice, sizeof(pciDevice));
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SaveState->Read(&pciFunction, sizeof(pciFunction));
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SaveState->Read(&pciReg, sizeof(pciReg));
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}
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/******************************************************************************
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Emulation Functions
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******************************************************************************/
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/*
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* CMPC10x::WritePCIConfigAddress(data):
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*
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* Writes to the PCI configuration space address (CONFIG_ADDR) register, which
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* selects a PCI device and configuration space register.
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*/
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void CMPC10x::WritePCIConfigAddress(UINT32 data)
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{
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UINT32 d = FLIPENDIAN32(data);
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pciBus = (d>>16)&0xFF;
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pciDevice = (d>>11)&0x1F;
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pciFunction = (d>>8)&7;
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pciReg = d&0xFF; // NOTE: for actual PCI devices (device>0), register must be shifted right by 2 and clamped to 0x3F
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// The manual is unclear as to whether device 0 (MPC10x) register #s are clamped to 0x3F or not. Pay attention to this!
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#ifdef DEBUG
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if (pciDevice == 0)
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{
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DebugLog("MPC10x: Device 0 configuration access: %08X\n", d);
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if ((d&3))
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ErrorLog("MPC10x: Device 0 configuration address with low bits set: %08X\n", d);
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}
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//DebugLog("MPC10x: Bus=%X, Device=%X, Function=%X, Reg=%X\n", pciBus, pciDevice, pciFunction, pciReg);
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#endif
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if (pciBus != 0)
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{
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//printf("Multiple PCI buses detected!\n");
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DebugLog("Multiple PCI buses detected!\n");
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}
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}
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/*
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* CMPC10x::ReadPCIConfigData(bits, offset):
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*
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* Reads from the PCI configuration space data (CONFIG_DATA) register, which in
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* turn calls upon the selected PCI device to return the data.
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*/
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UINT32 CMPC10x::ReadPCIConfigData(unsigned bits, unsigned offset)
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{
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// Handle self-access first
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if (pciDevice == 0)
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{
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// Alignment check
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#ifdef DEBUG
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if (((bits==16)&&(offset&1)) || ((bits==32)&&(offset&3)))
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ErrorLog("Misaligned MPC10x read request (bits=%d,reg=%X,offset=%d)\n", bits, pciReg, offset);
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#endif
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switch (bits)
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{
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case 8:
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return regs[pciReg+offset];
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case 16:
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return (regs[pciReg+offset+0]<<8) | regs[pciReg+offset+1];
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case 32:
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return (regs[pciReg+offset+0]<<24) |
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(regs[pciReg+offset+1]<<16) |
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(regs[pciReg+offset+2]<<8) |
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regs[pciReg+offset+3];
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default:
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ErrorLog("MPC10x internal error: invalid access size (%d-bits)", bits);
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break;
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}
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}
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// All other PCI devices passed to PCI bus
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return PCIBus->ReadConfigSpace(pciDevice, (pciReg>>2)&0x3C, bits, offset);
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}
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/*
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* CMPC10x::WritePCIConfigData(bits, offset, data):
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*
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* Writes to the PCI configuration space data (CONFIG_DATA) register, which in
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* turn passes the data to the selected PCI device.
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*/
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void CMPC10x::WritePCIConfigData(unsigned bits, unsigned offset, UINT32 data)
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{
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// Handle self-access first
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if (pciDevice == 0)
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{
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// Alignment check
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#ifdef DEBUG
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if (((bits==16)&&(offset&1)) || ((bits==32)&&(offset&3)))
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ErrorLog("Misaligned MPC10x read request (bits=%d,reg=%X,offset=%d)\n", bits, pciReg, offset);
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#endif
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switch (bits)
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{
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case 8:
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regs[pciReg+offset] = data&0xFF;
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break;
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case 16:
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regs[pciReg+offset+0] = (data>>8)&0xFF;
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regs[pciReg+offset+1] = data&0xFF;
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break;
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case 32:
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regs[pciReg+offset+0] = (data>>24)&0xFF;
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regs[pciReg+offset+1] = (data>>16)&0xFF;
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regs[pciReg+offset+2] = (data>>8)&0xFF;
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regs[pciReg+offset+3] = data&0xFF;
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break;
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default:
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ErrorLog("MPC10x internal error: invalid access size (%d-bits)", bits);
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break;
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}
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return;
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}
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PCIBus->WriteConfigSpace(pciDevice, (pciReg>>2)&0x3C, bits, offset, data);
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}
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/*
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* CMPC10x::WriteRegister(reg, data):
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*
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* Writes to the MPC10x register space. Accesses one byte at a time so it
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* should be endian-neutral (the caller ends up being responsible for this).
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*/
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void CMPC10x::WriteRegister(unsigned reg, UINT8 data)
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{
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regs[reg&0xFF] = data;
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if ((reg&0xFF)==0xA8)
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{
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if ((data&0x20))
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ErrorLog("MPC10x little endian mode not yet implemented!");
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}
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}
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/*
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* CMPC10x::Reset(void):
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*
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* Resets the device.
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*/
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void CMPC10x::Reset(void)
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{
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memset(regs, 0, sizeof(regs));
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// Data is actually stored in little endian format, so we can write directly here
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*(UINT16 *) ®s[0x00] = 0x1057; // vendor ID (Motorola)
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*(UINT16 *) ®s[0x02] = (model==0x106)?0x0002:0x0001; // device ID (MPC105 or MPC106)
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if (model == 0x106) // MPC106
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{
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*(UINT32 *) ®s[0x04] = 0x00800006; // PCI command and PCI status
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*(UINT32 *) ®s[0x08] = 0x00060000; // class code and revision ID
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*(UINT32 *) ®s[0x0C] = 0x00000800; // cache line size
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*(UINT32 *) ®s[0x70] = 0x00CD0000; // output driver control
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*(UINT32 *) ®s[0xA8] = 0x0010FF00; // processor interface config. 1
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*(UINT32 *) ®s[0xAC] = 0x060C000C; // processor interface config. 2
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*(UINT32 *) ®s[0xB8] = 0x04000000; // TO-DO: CHECK MANUAL
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*(UINT32 *) ®s[0xC0] = 0x00000100; // error enabling 1
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*(UINT32 *) ®s[0xE0] = 0x00420FFF; // emulation support configuration 1
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*(UINT32 *) ®s[0xE8] = 0x00200000; // emulation support configuration 2
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*(UINT32 *) ®s[0xF0] = 0x0000FF02; // memory control config. 1
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*(UINT32 *) ®s[0xF4] = 0x00030000; // memory control config. 2
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*(UINT32 *) ®s[0xFC] = 0x00000010; // memory control config. 4
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}
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else // MPC105
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{
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*(UINT32 *) ®s[0x04] = 0x00800006; // PCI command and PCI status
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*(UINT32 *) ®s[0x08] = 0x00060000; // class code and revision ID
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*(UINT32 *) ®s[0xA8] = 0x0010FF00; // processor interface config. 1
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*(UINT32 *) ®s[0xAC] = 0x060C000C; // processor interface config. 2
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*(UINT32 *) ®s[0xB8] = 0x04000000; // TO-DO: CHECK MANUAL
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*(UINT32 *) ®s[0xF0] = 0x0000FF02; // memory control config. 1
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*(UINT32 *) ®s[0xF4] = 0x00030000; // memory control config. 2
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*(UINT32 *) ®s[0xFC] = 0x00000010; // memory control config. 4
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// To-do: any more??
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}
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pciBus = 0;
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pciDevice = 0;
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pciFunction = 0;
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pciReg = 0;
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DebugLog("MPC%X reset\n", model);
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}
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/******************************************************************************
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Configuration, Initialization, and Shutdown
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******************************************************************************/
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/*
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* CMPC10x:AttachPCIBus(BusObjectPtr):
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*
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* Attaches a PCI bus object which will handle all PCI register requests.
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*/
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void CMPC10x::AttachPCIBus(CPCIBus *BusObjectPtr)
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{
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PCIBus = BusObjectPtr;
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DebugLog("MPC10x connected to a PCI bus\n");
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}
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/*
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* CMPC10x::SetModel(modelNum):
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*
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* Sets the device behavior to either MPC105 or MPC106.
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*/
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void CMPC10x::SetModel(int modelNum)
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{
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model = modelNum;
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if ((modelNum!=0x105) && (modelNum!=0x106))
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{
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ErrorLog("%s:%d: Invalid MPC10x model number (%X).", __FILE__, __LINE__, modelNum);
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model = 0x105;
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}
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DebugLog("MPC10x set to MPC%X\n", model);
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}
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/*
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* CMPC10x::Init():
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*
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* This must be called first and only once during the lifetime of the class.
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*/
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void CMPC10x::Init(void)
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{
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// this function really only exists for consistency with other device classes
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}
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/*
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* CMPC10x::CMPC10x(void):
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*
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* Constructor.
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*/
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CMPC10x::CMPC10x(void)
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{
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PCIBus = NULL;
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model = 0x105; // default to MPC105
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pciBus = 0;
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pciDevice = 0;
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pciFunction = 0;
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pciReg = 0;
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DebugLog("Built MPC10x\n");
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}
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/*
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* CMPC10x::~CMPC10x(void):
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*
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* Destructor.
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*/
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CMPC10x::~CMPC10x(void)
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{
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PCIBus = NULL;
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DebugLog("Destroyed MPC10x\n");
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}
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