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Misc: Use a 128b cache line size on Apple Silicon

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Turns out it's not 64 bytes like I assumed. The things you learn.
This commit is contained in:
Stenzek 2024-04-18 20:38:01 +10:00
parent fd21dd9729
commit 17b9736899
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2 changed files with 9 additions and 2 deletions
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7
src/common/types.h
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@ -185,6 +185,13 @@ static constexpr u32 HOST_PAGE_MASK = HOST_PAGE_SIZE - 1;
static constexpr u32 HOST_PAGE_SHIFT = 12;
#endif
// Host cache line sizes.
#if defined(__APPLE__) && defined(__aarch64__)
static constexpr u32 HOST_CACHE_LINE_SIZE = 128; // Apple Silicon uses 128b cache lines.
#else
static constexpr u32 HOST_CACHE_LINE_SIZE = 64; // Everything else is 64b.
#endif
// Enum class bitwise operators
#define IMPLEMENT_ENUM_CLASS_BITWISE_OPERATORS(type_) \
ALWAYS_INLINE constexpr type_ operator&(type_ lhs, type_ rhs) \

4
src/core/gpu_backend.h
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@ -83,8 +83,8 @@ protected:
};
FixedHeapArray<u8, COMMAND_QUEUE_SIZE> m_command_fifo_data;
alignas(64) std::atomic<u32> m_command_fifo_read_ptr{0};
alignas(64) std::atomic<u32> m_command_fifo_write_ptr{0};
alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_read_ptr{0};
alignas(HOST_CACHE_LINE_SIZE) std::atomic<u32> m_command_fifo_write_ptr{0};
};
#ifdef _MSC_VER