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Pad: Store JOY_BAUD

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This commit is contained in:
Connor McLaughlin 2019-10-18 23:10:41 +10:00
parent f046d1008e
commit 75f206262c
3 changed files with 16 additions and 11 deletions
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7
src/core/bus.cpp
View file

@ -137,7 +137,6 @@ TickCount Bus::ReadWords(PhysicalMemoryAddress address, u32* words, u32 word_cou
return total_ticks; return total_ticks;
} }
// DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock cycle per word (effectively around 17 // DMA is using DRAM Hyper Page mode, allowing it to access DRAM rows at 1 clock cycle per word (effectively around 17
// clks per 16 words, due to required row address loading, probably plus some further minimal overload due to refresh // clks per 16 words, due to required row address loading, probably plus some further minimal overload due to refresh
// cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle plus 6 // cycles). This is making DMA much faster than CPU memory accesses (CPU DRAM access takes 1 opcode cycle plus 6
@ -272,13 +271,13 @@ void Bus::RecalculateMemoryTimings()
std::tie(m_spu_access_time[0], m_spu_access_time[1], m_spu_access_time[2]) = std::tie(m_spu_access_time[0], m_spu_access_time[1], m_spu_access_time[2]) =
CalculateMemoryTiming(m_MEMCTRL.spu_delay_size, m_MEMCTRL.common_delay); CalculateMemoryTiming(m_MEMCTRL.spu_delay_size, m_MEMCTRL.common_delay);
Log_DevPrintf("BIOS Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", Log_TracePrintf("BIOS Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
m_MEMCTRL.bios_delay_size.data_bus_16bit ? 16 : 8, m_bios_access_time[0], m_bios_access_time[1], m_MEMCTRL.bios_delay_size.data_bus_16bit ? 16 : 8, m_bios_access_time[0], m_bios_access_time[1],
m_bios_access_time[2]); m_bios_access_time[2]);
Log_DevPrintf("CDROM Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", Log_TracePrintf("CDROM Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
m_MEMCTRL.cdrom_delay_size.data_bus_16bit ? 16 : 8, m_cdrom_access_time[0], m_cdrom_access_time[1], m_MEMCTRL.cdrom_delay_size.data_bus_16bit ? 16 : 8, m_cdrom_access_time[0], m_cdrom_access_time[1],
m_cdrom_access_time[2]); m_cdrom_access_time[2]);
Log_DevPrintf("SPU Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d", Log_TracePrintf("SPU Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
m_MEMCTRL.spu_delay_size.data_bus_16bit ? 16 : 8, m_spu_access_time[0], m_spu_access_time[1], m_MEMCTRL.spu_delay_size.data_bus_16bit ? 16 : 8, m_spu_access_time[0], m_spu_access_time[1],
m_spu_access_time[2]); m_spu_access_time[2]);
} }

7
src/core/pad.cpp
View file

@ -63,6 +63,7 @@ bool Pad::DoState(StateWrapper& sw)
sw.Do(&m_JOY_CTRL.bits); sw.Do(&m_JOY_CTRL.bits);
sw.Do(&m_JOY_STAT.bits); sw.Do(&m_JOY_STAT.bits);
sw.Do(&m_JOY_MODE.bits); sw.Do(&m_JOY_MODE.bits);
sw.Do(&m_JOY_BAUD);
sw.Do(&m_RX_FIFO); sw.Do(&m_RX_FIFO);
sw.Do(&m_TX_FIFO); sw.Do(&m_TX_FIFO);
return !sw.HasError(); return !sw.HasError();
@ -99,6 +100,9 @@ u32 Pad::ReadRegister(u32 offset)
case 0x0A: // JOY_CTRL case 0x0A: // JOY_CTRL
return ZeroExtend32(m_JOY_CTRL.bits); return ZeroExtend32(m_JOY_CTRL.bits);
case 0x0E: // JOY_BAUD
return ZeroExtend32(m_JOY_BAUD);
default: default:
Log_ErrorPrintf("Unknown register read: 0x%X", offset); Log_ErrorPrintf("Unknown register read: 0x%X", offset);
return UINT32_C(0xFFFFFFFF); return UINT32_C(0xFFFFFFFF);
@ -167,7 +171,8 @@ void Pad::WriteRegister(u32 offset, u32 value)
case 0x0E: case 0x0E:
{ {
Log_WarningPrintf("JOY_BAUD <- 0x%08X", value); Log_DebugPrintf("JOY_BAUD <- 0x%08X", value);
m_JOY_BAUD = value;
return; return;
} }

1
src/core/pad.h
View file

@ -110,6 +110,7 @@ private:
JOY_CTRL m_JOY_CTRL = {}; JOY_CTRL m_JOY_CTRL = {};
JOY_STAT m_JOY_STAT = {}; JOY_STAT m_JOY_STAT = {};
JOY_MODE m_JOY_MODE = {}; JOY_MODE m_JOY_MODE = {};
u16 m_JOY_BAUD = 0;
ActiveDevice m_active_device = ActiveDevice::None; ActiveDevice m_active_device = ActiveDevice::None;
InlineFIFOQueue<u8, 8> m_RX_FIFO; InlineFIFOQueue<u8, 8> m_RX_FIFO;