CPU: Fix InterpretUncachedBlock()

But this shouldn't be hit during normal execution.
This commit is contained in:
Connor McLaughlin 2020-09-19 21:21:29 +10:00
parent 1d5af57f71
commit 9736dc7895

View file

@ -1461,7 +1461,8 @@ template void InterpretCachedBlock<PGXPMode::CPU>(const CodeBlock& block);
void InterpretUncachedBlock() void InterpretUncachedBlock()
{ {
Panic("Fixme with regards to re-fetching PC"); g_state.regs.npc = g_state.regs.pc;
FetchInstruction();
// At this point, pc contains the last address executed (in the previous block). The instruction has not been fetched // At this point, pc contains the last address executed (in the previous block). The instruction has not been fetched
// yet. pc shouldn't be updated until the fetch occurs, that way the exception occurs in the delay slot. // yet. pc shouldn't be updated until the fetch occurs, that way the exception occurs in the delay slot.
@ -1480,8 +1481,15 @@ void InterpretUncachedBlock()
g_state.exception_raised = false; g_state.exception_raised = false;
// Fetch the next instruction, except if we're in a branch delay slot. The "fetch" is done in the next block. // Fetch the next instruction, except if we're in a branch delay slot. The "fetch" is done in the next block.
if (!g_state.current_instruction_in_branch_delay_slot)
{
if (!FetchInstruction()) if (!FetchInstruction())
break; break;
}
else
{
g_state.regs.pc = g_state.regs.npc;
}
// execute the instruction we previously fetched // execute the instruction we previously fetched
ExecuteInstruction<PGXPMode::Disabled>(); ExecuteInstruction<PGXPMode::Disabled>();