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CPU: Fix InterpretUncachedBlock()
But this shouldn't be hit during normal execution.
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@ -1461,7 +1461,8 @@ template void InterpretCachedBlock<PGXPMode::CPU>(const CodeBlock& block);
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void InterpretUncachedBlock()
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void InterpretUncachedBlock()
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{
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{
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Panic("Fixme with regards to re-fetching PC");
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g_state.regs.npc = g_state.regs.pc;
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FetchInstruction();
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// At this point, pc contains the last address executed (in the previous block). The instruction has not been fetched
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// At this point, pc contains the last address executed (in the previous block). The instruction has not been fetched
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// yet. pc shouldn't be updated until the fetch occurs, that way the exception occurs in the delay slot.
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// yet. pc shouldn't be updated until the fetch occurs, that way the exception occurs in the delay slot.
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@ -1480,8 +1481,15 @@ void InterpretUncachedBlock()
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g_state.exception_raised = false;
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g_state.exception_raised = false;
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// Fetch the next instruction, except if we're in a branch delay slot. The "fetch" is done in the next block.
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// Fetch the next instruction, except if we're in a branch delay slot. The "fetch" is done in the next block.
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if (!FetchInstruction())
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if (!g_state.current_instruction_in_branch_delay_slot)
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break;
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{
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if (!FetchInstruction())
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break;
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}
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else
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{
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g_state.regs.pc = g_state.regs.npc;
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}
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// execute the instruction we previously fetched
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// execute the instruction we previously fetched
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ExecuteInstruction<PGXPMode::Disabled>();
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ExecuteInstruction<PGXPMode::Disabled>();
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