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CPU: Implement sub instruction
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parent
1afa02d475
commit
ced3038e73
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@ -206,6 +206,11 @@ static constexpr bool AddOverflow(u32 old_value, u32 add_value, u32 new_value)
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return (((new_value ^ old_value) & (new_value ^ add_value)) & UINT32_C(0x80000000)) != 0;
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return (((new_value ^ old_value) & (new_value ^ add_value)) & UINT32_C(0x80000000)) != 0;
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}
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}
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static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u32 new_value)
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{
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return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
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}
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void Core::DisassembleAndPrint(u32 addr)
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void Core::DisassembleAndPrint(u32 addr)
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{
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{
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u32 bits;
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u32 bits;
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@ -358,6 +363,21 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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}
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}
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break;
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break;
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case InstructionFunct::sub:
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{
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const u32 old_value = ReadReg(inst.r.rs);
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const u32 sub_value = ReadReg(inst.r.rt);
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const u32 new_value = old_value - sub_value;
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if (SubOverflow(old_value, sub_value, new_value))
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{
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RaiseException(inst_pc, Exception::Ov);
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return;
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}
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WriteReg(inst.r.rd, new_value);
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}
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break;
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case InstructionFunct::subu:
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case InstructionFunct::subu:
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{
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{
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const u32 new_value = ReadReg(inst.r.rs) - ReadReg(inst.r.rt);
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const u32 new_value = ReadReg(inst.r.rs) - ReadReg(inst.r.rt);
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