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CPU: Fix load delay register reads for same register in delay slot

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This commit is contained in:
Connor McLaughlin 2019-09-15 12:16:51 +10:00
parent 1bb794dd39
commit d58dbe04c0
2 changed files with 11 additions and 3 deletions
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11
src/pse/cpu_core.cpp
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@ -179,13 +179,18 @@ void Core::RaiseException(Exception excode)
FlushPipeline();
}
void Core::FlushPipeline()
void Core::FlushLoadDelay()
{
// loads are flushed
m_load_delay_reg = Reg::count;
m_load_delay_old_value = 0;
m_next_load_delay_reg = Reg::count;
m_next_load_delay_old_value = 0;
}
void Core::FlushPipeline()
{
// loads are flushed
FlushLoadDelay();
// not in a branch delay slot
m_branched = false;
@ -214,7 +219,7 @@ void Core::WriteRegDelayed(Reg rd, u32 value)
// save the old value, this will be returned if the register is read in the next instruction
m_next_load_delay_reg = rd;
m_next_load_delay_old_value = m_regs.r[static_cast<u8>(rd)];
m_next_load_delay_old_value = ReadReg(rd);
m_regs.r[static_cast<u8>(rd)] = value;
}

3
src/pse/cpu_core.h
View file

@ -71,6 +71,9 @@ private:
void Branch(u32 target);
void RaiseException(Exception excode);
// flushes any load delays if present
void FlushLoadDelay();
// clears pipeline of load/branch delays
void FlushPipeline();