Xargon/Duckstation
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18 commits

Author SHA1 Message Date
Stenzek 32f5482ad2
CPU: Inhibit debug dispatcher when COP0 BP is invalid 2024-01-01 15:25:48 +10:00
Stenzek 56fc207af6 CPU: Use lookup tables for memory access 2023-10-01 20:48:02 +10:00
Stenzek 199c53f3af BIOS: Replace TTY patch with syscall hook 2023-08-30 00:44:01 +10:00
Stenzek 5b980dafa5 System: Refactor main loop 
Reduces JIT exits.
Improves runahead performance.
 2023-08-16 01:13:00 +10:00
Stenzek 84e5fbe0c6 CPU: HLE implementation of PCDrv (host file access) 2023-04-29 20:45:39 +10:00
Connor McLaughlin 8c7a192128 Misc: Add copyright/license statement to applicable files 
Should've did this in the beginning.
 2022-12-04 21:03:49 +10:00
Connor McLaughlin 30db081a64 CPU: Simulate stalls from GTE instructions 2021-07-16 12:27:31 +10:00
Connor McLaughlin 1ed1d641a6 CPU/Recompiler: Don't use intepreter icache when falling back 
Fixes broken rendering in TOCA 2.

It has self-modifying code every frame, which gets falled back to the
interpreter, and using the interpreter's icache, which resulted in
stale code executing.
 2021-05-20 12:19:23 +10:00
Connor McLaughlin 40731b49fc Bus: Handle CPU-internal narrow writes 
The full 32-bits of the GPR are used.

Fixes SoundScope in the BIOS Shell.
 2021-04-26 22:08:18 +10:00
Connor McLaughlin 442b801d39 CPU: Implement cop0 execution and data breakpoints 2021-04-14 19:06:52 +10:00
Connor McLaughlin 701edb335a Various warning fixes 2021-02-06 19:19:55 +10:00
Connor McLaughlin e044858953 CPU: Add additional instruction decoder helpers 2020-12-17 11:57:46 +10:00
Connor McLaughlin be63d893cd CPU: Use partial icache fills for non-line-aligned addresses 2020-10-30 00:44:40 +10:00
Connor McLaughlin cb351a7dbd CPU: Move interrupt check out of inner-most exec loop 2020-10-18 14:54:38 +10:00
Connor McLaughlin 0afdc04d88 CPU/Recompiler: Optimize constant reads (and some writes) 2020-10-18 14:54:38 +10:00
Connor McLaughlin 19d6037b99 CPU: Implement instruction cache simulation 
Implemented for all execution modes. Disabled by default in the cached
interpreter and recompiler, always enabled in the pure interpreter.
 2020-08-29 22:07:40 +10:00
Connor McLaughlin 1d5f810a4b CPU/Recompiler: Disable memory access exceptions by default 
This means it'll no longer pass amidog's CPU test in the default config.
But no games rely on this. You can enable it in advanced options if you
want to pass the CPU test.
 2020-08-08 23:44:13 +10:00
Connor McLaughlin f6e88353eb CPU/Recompiler: Make generated code invariant to virtual PC 2020-08-08 23:06:28 +10:00