mirror of
https://github.com/RetroDECK/Duckstation.git
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129 lines
3.7 KiB
C++
129 lines
3.7 KiB
C++
#pragma once
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#include "common/bitfield.h"
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#include "cpu_types.h"
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#include "gte_types.h"
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#include "types.h"
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#include <array>
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#include <optional>
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class StateWrapper;
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namespace CPU {
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enum : VirtualMemoryAddress
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{
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RESET_VECTOR = UINT32_C(0xBFC00000)
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};
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enum : PhysicalMemoryAddress
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{
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DCACHE_LOCATION = UINT32_C(0x1F800000),
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DCACHE_LOCATION_MASK = UINT32_C(0xFFFFFC00),
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DCACHE_OFFSET_MASK = UINT32_C(0x000003FF),
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DCACHE_SIZE = UINT32_C(0x00000400),
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ICACHE_SIZE = UINT32_C(0x00001000),
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ICACHE_SLOTS = ICACHE_SIZE / sizeof(u32),
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ICACHE_LINE_SIZE = 16,
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ICACHE_LINES = ICACHE_SIZE / ICACHE_LINE_SIZE,
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ICACHE_SLOTS_PER_LINE = ICACHE_SLOTS / ICACHE_LINES,
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ICACHE_TAG_ADDRESS_MASK = 0xFFFFFFF0u,
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ICACHE_INVALID_BITS = 0x0Fu,
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};
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union CacheControl
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{
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u32 bits;
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BitField<u32, bool, 0, 1> lock_mode;
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BitField<u32, bool, 1, 1> invalidate_mode;
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BitField<u32, bool, 2, 1> tag_test_mode;
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BitField<u32, bool, 3, 1> dcache_scratchpad;
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BitField<u32, bool, 7, 1> dcache_enable;
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BitField<u32, u8, 8, 2> icache_fill_size; // actually dcache? icache always fills to 16 bytes
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BitField<u32, bool, 11, 1> icache_enable;
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};
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struct State
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{
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// ticks the CPU has executed
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TickCount pending_ticks = 0;
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TickCount downcount = 0;
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Registers regs = {};
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Cop0Registers cop0_regs = {};
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Instruction next_instruction = {};
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// address of the instruction currently being executed
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Instruction current_instruction = {};
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u32 current_instruction_pc = 0;
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bool current_instruction_in_branch_delay_slot = false;
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bool current_instruction_was_branch_taken = false;
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bool next_instruction_is_branch_delay_slot = false;
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bool branch_was_taken = false;
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bool exception_raised = false;
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bool interrupt_delay = false;
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bool frame_done = false;
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// load delays
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Reg load_delay_reg = Reg::count;
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u32 load_delay_value = 0;
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Reg next_load_delay_reg = Reg::count;
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u32 next_load_delay_value = 0;
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CacheControl cache_control{ 0 };
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// GTE registers are stored here so we can access them on ARM with a single instruction
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GTE::Regs gte_regs = {};
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u8* fastmem_base = nullptr;
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// data cache (used as scratchpad)
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std::array<u8, DCACHE_SIZE> dcache = {};
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std::array<u32, ICACHE_LINES> icache_tags = {};
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std::array<u8, ICACHE_SIZE> icache_data = {};
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};
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extern State g_state;
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void Initialize();
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void Shutdown();
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void Reset();
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bool DoState(StateWrapper& sw);
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void ClearICache();
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/// Executes interpreter loop.
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void Execute();
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ALWAYS_INLINE Registers& GetRegs() { return g_state.regs; }
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ALWAYS_INLINE TickCount GetPendingTicks() { return g_state.pending_ticks; }
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ALWAYS_INLINE void ResetPendingTicks() { g_state.pending_ticks = 0; }
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ALWAYS_INLINE void AddPendingTicks(TickCount ticks) { g_state.pending_ticks += ticks; }
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// state helpers
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ALWAYS_INLINE bool InUserMode() { return g_state.cop0_regs.sr.KUc; }
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ALWAYS_INLINE bool InKernelMode() { return !g_state.cop0_regs.sr.KUc; }
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// Memory reads variants which do not raise exceptions.
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bool SafeReadMemoryByte(VirtualMemoryAddress addr, u8* value);
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bool SafeReadMemoryHalfWord(VirtualMemoryAddress addr, u16* value);
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bool SafeReadMemoryWord(VirtualMemoryAddress addr, u32* value);
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bool SafeWriteMemoryByte(VirtualMemoryAddress addr, u8 value);
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bool SafeWriteMemoryHalfWord(VirtualMemoryAddress addr, u16 value);
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bool SafeWriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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// External IRQs
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void SetExternalInterrupt(u8 bit);
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void ClearExternalInterrupt(u8 bit);
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void DisassembleAndPrint(u32 addr);
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void DisassembleAndLog(u32 addr);
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void DisassembleAndPrint(u32 addr, u32 instructions_before, u32 instructions_after);
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// Write to CPU execution log file.
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void WriteToExecutionLog(const char* format, ...);
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extern bool TRACE_EXECUTION;
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extern bool LOG_EXECUTION;
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} // namespace CPU
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