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https://github.com/RetroDECK/Duckstation.git
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128 lines
4.1 KiB
C++
128 lines
4.1 KiB
C++
// SPDX-FileCopyrightText: 2019-2022 Connor McLaughlin <stenzek@gmail.com>
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// SPDX-License-Identifier: (GPL-3.0 OR CC-BY-NC-ND-4.0)
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#pragma once
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#include "bus.h"
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#include "cpu_core.h"
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namespace CPU {
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// exceptions
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void RaiseException(Exception excode);
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void RaiseException(u32 CAUSE_bits, u32 EPC);
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void RaiseBreakException(u32 CAUSE_bits, u32 EPC, u32 instruction_bits);
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ALWAYS_INLINE static bool HasPendingInterrupt()
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{
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return g_state.cop0_regs.sr.IEc &&
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(((g_state.cop0_regs.cause.bits & g_state.cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0);
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}
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ALWAYS_INLINE static void CheckForPendingInterrupt()
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{
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if (HasPendingInterrupt())
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g_state.downcount = 0;
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}
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void DispatchInterrupt();
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void UpdateDebugDispatcherFlag();
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// icache stuff
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ALWAYS_INLINE static bool IsCachedAddress(VirtualMemoryAddress address)
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{
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// KUSEG, KSEG0
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return (address >> 29) <= 4;
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}
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ALWAYS_INLINE static u32 GetICacheLine(VirtualMemoryAddress address)
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{
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return ((address >> 4) & 0xFFu);
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}
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ALWAYS_INLINE static u32 GetICacheLineOffset(VirtualMemoryAddress address)
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{
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return (address & (ICACHE_LINE_SIZE - 1));
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}
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ALWAYS_INLINE static u32 GetICacheTagForAddress(VirtualMemoryAddress address)
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{
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return (address & ICACHE_TAG_ADDRESS_MASK);
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}
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ALWAYS_INLINE static u32 GetICacheFillTagForAddress(VirtualMemoryAddress address)
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{
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static const u32 invalid_bits[4] = {0, 1, 3, 7};
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return GetICacheTagForAddress(address) | invalid_bits[(address >> 2) & 0x03u];
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}
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ALWAYS_INLINE static u32 GetICacheTagMaskForAddress(VirtualMemoryAddress address)
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{
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static const u32 mask[4] = {ICACHE_TAG_ADDRESS_MASK | 1, ICACHE_TAG_ADDRESS_MASK | 2, ICACHE_TAG_ADDRESS_MASK | 4,
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ICACHE_TAG_ADDRESS_MASK | 8};
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return mask[(address >> 2) & 0x03u];
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}
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ALWAYS_INLINE static bool CompareICacheTag(VirtualMemoryAddress address)
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{
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const u32 line = GetICacheLine(address);
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return ((g_state.icache_tags[line] & GetICacheTagMaskForAddress(address)) == GetICacheTagForAddress(address));
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}
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TickCount GetInstructionReadTicks(VirtualMemoryAddress address);
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TickCount GetICacheFillTicks(VirtualMemoryAddress address);
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u32 FillICache(VirtualMemoryAddress address);
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void CheckAndUpdateICacheTags(u32 line_count, TickCount uncached_ticks);
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ALWAYS_INLINE static Segment GetSegmentForAddress(VirtualMemoryAddress address)
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{
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switch ((address >> 29))
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{
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case 0x00: // KUSEG 0M-512M
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case 0x01: // KUSEG 512M-1024M
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case 0x02: // KUSEG 1024M-1536M
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case 0x03: // KUSEG 1536M-2048M
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return Segment::KUSEG;
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case 0x04: // KSEG0 - physical memory cached
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return Segment::KSEG0;
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case 0x05: // KSEG1 - physical memory uncached
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return Segment::KSEG1;
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case 0x06: // KSEG2
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case 0x07: // KSEG2
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default:
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return Segment::KSEG2;
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}
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}
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ALWAYS_INLINE static constexpr PhysicalMemoryAddress VirtualAddressToPhysical(VirtualMemoryAddress address)
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{
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return (address & PHYSICAL_MEMORY_ADDRESS_MASK);
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}
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ALWAYS_INLINE static VirtualMemoryAddress PhysicalAddressToVirtual(PhysicalMemoryAddress address, Segment segment)
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{
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static constexpr std::array<VirtualMemoryAddress, 4> bases = {{0x00000000, 0x80000000, 0xA0000000, 0xE0000000}};
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return bases[static_cast<u32>(segment)] | address;
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}
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Bus::MemoryReadHandler GetMemoryReadHandler(VirtualMemoryAddress address, MemoryAccessSize size);
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Bus::MemoryWriteHandler GetMemoryWriteHandler(VirtualMemoryAddress address, MemoryAccessSize size);
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// memory access functions which return false if an exception was thrown.
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bool SafeReadInstruction(VirtualMemoryAddress addr, u32* value);
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void* GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size, TickCount* read_ticks);
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void* GetDirectWriteMemoryPointer(VirtualMemoryAddress address, MemoryAccessSize size);
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ALWAYS_INLINE static void AddGTETicks(TickCount ticks)
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{
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g_state.gte_completion_tick = g_state.pending_ticks + ticks + 1;
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}
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ALWAYS_INLINE static void StallUntilGTEComplete()
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{
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g_state.pending_ticks =
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(g_state.gte_completion_tick > g_state.pending_ticks) ? g_state.gte_completion_tick : g_state.pending_ticks;
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}
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// kernel call interception
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void HandleA0Syscall();
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void HandleB0Syscall();
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} // namespace CPU
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