2021-04-14 01:20:45 +00:00
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/**
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** Supermodel
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** A Sega Model 3 Arcade Emulator.
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** Copyright 2011-2020 Bart Trzynadlowski, Nik Henson, Ian Curtis,
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** Harry Tuttle, and Spindizzi
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**
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** This file is part of Supermodel.
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**
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** Supermodel is free software: you can redistribute it and/or modify it under
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** the terms of the GNU General Public License as published by the Free
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** Software Foundation, either version 3 of the License, or (at your option)
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** any later version.
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**
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** Supermodel is distributed in the hope that it will be useful, but WITHOUT
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** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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** more details.
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**
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** You should have received a copy of the GNU General Public License along
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** with Supermodel. If not, see <http://www.gnu.org/licenses/>.
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**/
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#include <chrono>
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#include <thread>
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#include "Supermodel.h"
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#include "SimNetBoard.h"
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// these make 16-bit read/writes much neater
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#define RAM16 *(uint16_t*)&RAM
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#define CommRAM16 *(uint16_t*)&CommRAM
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static const uint64_t netGUID = 0x5bf177da34872;
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inline bool CSimNetBoard::IsGame(const char* gameName)
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{
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return (m_gameInfo.name == gameName) || (m_gameInfo.parent == gameName);
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}
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CSimNetBoard::CSimNetBoard(const Util::Config::Node& config) : m_config(config)
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{
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}
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CSimNetBoard::~CSimNetBoard(void)
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{
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2021-10-30 23:00:49 +00:00
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m_quit = true;
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2021-04-14 01:20:45 +00:00
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if (m_connectThread.joinable())
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m_connectThread.join();
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}
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void CSimNetBoard::SaveState(CBlockFile* SaveState)
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{
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}
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void CSimNetBoard::LoadState(CBlockFile* SaveState)
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{
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}
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bool CSimNetBoard::Init(uint8_t* netRAMPtr, uint8_t* netBufferPtr)
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{
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RAM = netRAMPtr;
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2021-11-05 00:23:29 +00:00
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Buffer = netBufferPtr;
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CommRAM = Buffer;
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externalCommRAM = Buffer + 0x10000;
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2021-04-14 01:20:45 +00:00
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m_attached = m_gameInfo.netboard_present && m_config["Network"].ValueAs<bool>();
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if (!m_attached)
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return 0;
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if (IsGame("daytona2") || IsGame("harley") || IsGame("scud") || IsGame("srally2") ||
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IsGame("skichamp") || IsGame("spikeout") || IsGame("spikeofe"))
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m_gameType = GameType::one;
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else if (IsGame("lemans24") || IsGame("von2") || IsGame("dirtdvls"))
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m_gameType = GameType::two;
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else
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return ErrorLog("Game not recognized or supported");
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m_state = State::start;
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//netsocks
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port_in = m_config["PortIn"].ValueAs<unsigned>();
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port_out = m_config["PortOut"].ValueAs<unsigned>();
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addr_out = m_config["AddressOut"].ValueAs<std::string>();
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nets = std::make_unique<TCPSend>(addr_out, port_out);
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netr = std::make_unique<TCPReceive>(port_in);
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return 0;
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}
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void CSimNetBoard::RunFrame(void)
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{
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if (!IsRunning())
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return;
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switch (m_state)
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{
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case State::start:
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if (!m_connected && !m_connectThread.joinable())
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m_connectThread = std::thread(&CSimNetBoard::ConnectProc, this);
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2021-10-30 23:00:49 +00:00
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m_status0 = 0;
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m_status1 = IsGame("dirtdvls") ? 0x4004 : 0xe000;
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2021-04-14 01:20:45 +00:00
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m_state = State::init;
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break;
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case State::init:
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2021-11-05 00:23:29 +00:00
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memset(CommRAM, 0, 0x20000);
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2021-04-14 01:20:45 +00:00
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if (m_gameType == GameType::one)
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{
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2021-10-30 23:00:49 +00:00
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if (m_status0 & 0x8000) // has main board changed this register?
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2021-04-14 01:20:45 +00:00
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{
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2021-10-30 23:00:49 +00:00
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m_IRQ2ack |= 0x01; // simulate IRQ 2 ack
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if (m_status0 == 0xf000)
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2021-04-14 01:20:45 +00:00
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{
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// initialization complete
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2021-10-30 23:00:49 +00:00
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m_status1 = 0;
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2021-04-14 01:20:45 +00:00
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CommRAM16[0x72] = FLIPENDIAN16(0x1); // is this necessary?
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m_state = State::testing;
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}
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2021-10-30 23:00:49 +00:00
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m_status0 = 0; // 0 should work for all init subroutines
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2021-04-14 01:20:45 +00:00
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}
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}
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else
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{
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// type 2 performs initialization on its own
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2021-10-30 23:00:49 +00:00
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m_status1 = 0;
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2021-04-14 01:20:45 +00:00
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m_state = State::testing;
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m_counter = 0;
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}
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break;
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case State::testing:
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if (m_gameType == GameType::one)
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{
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2021-10-30 23:00:49 +00:00
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m_status0 += 1; // type 1 games require this to be incremented every frame
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2021-04-14 01:20:45 +00:00
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if (!m_connected)
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break;
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uint8_t numMachines, machineIndex;
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if (RAM16[0x400] == 0) // master
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{
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// flush receive buffer
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while (netr->CheckDataAvailable())
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{
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netr->Receive();
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}
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// check all linked instances have the same GUID
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nets->Send(&netGUID, sizeof(netGUID));
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auto& recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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uint64_t testGUID;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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// send the GUID for one more loop
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nets->Send(&testGUID, sizeof(testGUID));
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netr->Receive();
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if (testGUID != netGUID)
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{
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ErrorLog("unable to verify connection. Make sure all machines are using same build!");
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m_state = State::error;
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break;
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}
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// master has an index of zero
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machineIndex = 0;
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nets->Send(&machineIndex, sizeof(machineIndex));
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// receive back the number of other linked machines
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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numMachines = recv_data[0];
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// send the number of other linked machines
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nets->Send(&numMachines, sizeof(numMachines));
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netr->Receive();
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}
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else
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{
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// receive GUID from the previous machine and check it matches
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auto& recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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uint64_t testGUID;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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nets->Send(&testGUID, sizeof(testGUID));
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// one more time, in case a later machine has a GUID mismatch
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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nets->Send(&testGUID, sizeof(testGUID));
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if (testGUID != netGUID)
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{
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ErrorLog("unable to verify connection. Make sure all machines are using same build!");
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m_state = State::error;
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break;
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}
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// receive the previous machine's index, increment it, send it to the next machine
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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machineIndex = recv_data[0] + 1;
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nets->Send(&machineIndex, sizeof(machineIndex));
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// receive the number of other linked machines and forward it on
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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numMachines = recv_data[0];
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nets->Send(&numMachines, sizeof(numMachines));
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}
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2021-04-19 22:15:50 +00:00
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// if there are no other linked machines, only continue if Supermodel is linked to itself
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// there might be more than one machine set to master which would cause glitches
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if ((numMachines == 0) && ((port_in != port_out) || (addr_out.compare("127.0.0.1") != 0)))
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{
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ErrorLog("no slave machines detected. Make sure only one machine is set to master!");
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m_state = State::error;
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break;
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}
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2021-04-14 01:20:45 +00:00
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m_numMachines = numMachines + 1;
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2021-10-30 23:00:49 +00:00
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m_status0 = 0; // supposed to cycle between 0 and 1 (also 2 for Daytona 2); doesn't seem to matter
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m_status1 = 0x2021 + (numMachines * 0x20) + machineIndex;
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2021-04-14 01:20:45 +00:00
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CommRAM16[0x0] = RAM16[0x400]; // 0 if master, 1 if slave
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CommRAM16[0x2] = numMachines;
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CommRAM16[0x4] = machineIndex;
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m_counter = 0;
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CommRAM16[0x6] = 0;
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m_segmentSize = RAM16[0x404];
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// don't know if these are actually required, but it never hurts to include them
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CommRAM16[0x8] = FLIPENDIAN16(0x100 + m_segmentSize);
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CommRAM16[0xa] = FLIPENDIAN16(RAM16[0x402] - m_segmentSize - 1);
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CommRAM16[0xc] = FLIPENDIAN16(0x100);
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CommRAM16[0xe] = FLIPENDIAN16(RAM16[0x402] - m_segmentSize + 0x200);
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m_state = State::ready;
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}
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else
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{
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if (!m_connected)
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break;
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// we have to track both playable and non-playable machines for type 2
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struct
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{
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uint8_t total;
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uint8_t playable;
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} numMachines, machineIndex;
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if (RAM16[0x200] == 0) // master
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{
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// flush receive buffer
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while (netr->CheckDataAvailable())
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netr->Receive();
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// check all linked instances have the same GUID
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nets->Send(&netGUID, sizeof(netGUID));
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auto& recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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uint64_t testGUID;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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// send the GUID for one more loop
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nets->Send(&testGUID, sizeof(testGUID));
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netr->Receive();
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if (testGUID != netGUID)
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{
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ErrorLog("unable to verify connection. Make sure all machines are using same build!");
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m_state = State::error;
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break;
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}
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// master has indices set to zero
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machineIndex.total = 0, machineIndex.playable = 0;
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nets->Send(&machineIndex, sizeof(machineIndex));
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// receive back the number of other linked machines
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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memcpy(&numMachines, &recv_data[0], recv_data.size());
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// send the number of other linked machines
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nets->Send(&numMachines, sizeof(numMachines));
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netr->Receive();
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}
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else if (RAM16[0x200] < 0x8000) // slave
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{
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// receive GUID from the previous machine and check it matches
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auto& recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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uint64_t testGUID;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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nets->Send(&testGUID, sizeof(testGUID));
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// one more time, in case a later machine has a GUID mismatch
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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memcpy(&testGUID, &recv_data[0], recv_data.size());
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if (testGUID != netGUID)
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testGUID = 0;
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nets->Send(&testGUID, sizeof(testGUID));
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if (testGUID != netGUID)
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{
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ErrorLog("unable to verify connection. Make sure all machines are using same build!");
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m_state = State::error;
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break;
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}
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// receive the indices of the previous machine and increment them
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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memcpy(&machineIndex, &recv_data[0], recv_data.size());
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machineIndex.total++, machineIndex.playable++;
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// send our indices to the next machine
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nets->Send(&machineIndex, sizeof(machineIndex));
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// receive the number of machines
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recv_data = netr->Receive();
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if (recv_data.empty())
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break;
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memcpy(&numMachines, &recv_data[0], recv_data.size());
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// forward the number of machines
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nets->Send(&numMachines, sizeof(numMachines));
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}
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else
|
|
|
|
{
|
|
|
|
// relay/satellite
|
|
|
|
|
|
|
|
// receive GUID from the previous machine and check it matches
|
|
|
|
auto& recv_data = netr->Receive();
|
|
|
|
if (recv_data.empty())
|
|
|
|
break;
|
|
|
|
uint64_t testGUID;
|
|
|
|
memcpy(&testGUID, &recv_data[0], recv_data.size());
|
|
|
|
if (testGUID != netGUID)
|
|
|
|
testGUID = 0;
|
|
|
|
nets->Send(&testGUID, sizeof(testGUID));
|
|
|
|
|
|
|
|
// one more time, in case a later machine has a GUID mismatch
|
|
|
|
recv_data = netr->Receive();
|
|
|
|
if (recv_data.empty())
|
|
|
|
break;
|
|
|
|
memcpy(&testGUID, &recv_data[0], recv_data.size());
|
|
|
|
if (testGUID != netGUID)
|
|
|
|
testGUID = 0;
|
|
|
|
nets->Send(&testGUID, sizeof(testGUID));
|
|
|
|
|
|
|
|
if (testGUID != netGUID)
|
|
|
|
{
|
|
|
|
ErrorLog("unable to verify connection. Make sure all machines are using same build!");
|
|
|
|
m_state = State::error;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// receive the indices of the previous machine; don't increment the playable index
|
|
|
|
recv_data = netr->Receive();
|
|
|
|
if (recv_data.empty())
|
|
|
|
break;
|
|
|
|
memcpy(&machineIndex, &recv_data[0], recv_data.size());
|
|
|
|
machineIndex.total++;
|
|
|
|
|
|
|
|
// send our indices to the next machine
|
|
|
|
nets->Send(&machineIndex, sizeof(machineIndex));
|
|
|
|
|
|
|
|
// receive the number of machines
|
|
|
|
recv_data = netr->Receive();
|
|
|
|
if (recv_data.empty())
|
|
|
|
break;
|
|
|
|
memcpy(&numMachines, &recv_data[0], recv_data.size());
|
|
|
|
|
|
|
|
// forward the number of machines
|
|
|
|
nets->Send(&numMachines, sizeof(numMachines));
|
|
|
|
|
|
|
|
// indicate that this machine is a relay/satellite
|
|
|
|
if (!IsGame("dirtdvls"))
|
|
|
|
machineIndex.playable |= 0x80;
|
|
|
|
}
|
|
|
|
|
|
|
|
// if there are no other linked machines, only continue if Supermodel is linked to itself
|
|
|
|
// there might be more than one machine set to master which would cause glitches
|
2021-04-19 22:15:50 +00:00
|
|
|
if ((numMachines.total == 0) && ((port_in != port_out) || (addr_out.compare("127.0.0.1") != 0)))
|
2021-04-14 01:20:45 +00:00
|
|
|
{
|
|
|
|
ErrorLog("no slave machines detected. Make sure only one machine is set to master!");
|
|
|
|
if (IsGame("dirtdvls"))
|
2021-10-30 23:00:49 +00:00
|
|
|
m_status1 = 0x8085; // seems like the netboard code writers really liked their CPU model numbers
|
2021-04-14 01:20:45 +00:00
|
|
|
m_state = State::error;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
m_numMachines = numMachines.total + 1;
|
|
|
|
|
2021-10-30 23:00:49 +00:00
|
|
|
m_status0 = 5; // probably not necessary
|
2021-04-14 01:20:45 +00:00
|
|
|
if (IsGame("dirtdvls"))
|
2021-10-30 23:00:49 +00:00
|
|
|
m_status1 = (numMachines.playable << 4) | machineIndex.playable | 0x7400;
|
2021-04-14 01:20:45 +00:00
|
|
|
else
|
2021-10-30 23:00:49 +00:00
|
|
|
m_status1 = (numMachines.playable << 8) | machineIndex.playable;
|
2021-04-14 01:20:45 +00:00
|
|
|
|
|
|
|
CommRAM16[0x0] = RAM16[0x200]; // master/slave/relay status
|
|
|
|
CommRAM16[0x2] = (numMachines.playable << 8) | numMachines.total;
|
|
|
|
CommRAM16[0x4] = (machineIndex.playable << 8) | machineIndex.total;
|
|
|
|
|
|
|
|
m_counter = 0;
|
|
|
|
CommRAM16[0x6] = 0;
|
|
|
|
|
|
|
|
m_segmentSize = RAM16[0x204];
|
|
|
|
|
|
|
|
// don't know if these are actually required, but it never hurts to include them
|
|
|
|
CommRAM16[0x8] = FLIPENDIAN16(0x100 + m_segmentSize);
|
|
|
|
CommRAM16[0xa] = FLIPENDIAN16(RAM16[0x206]);
|
|
|
|
CommRAM16[0xc] = FLIPENDIAN16(0x100);
|
|
|
|
CommRAM16[0xe] = FLIPENDIAN16(RAM16[0x206] + 0x80);
|
|
|
|
|
|
|
|
m_state = State::ready;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case State::ready:
|
|
|
|
m_counter++;
|
|
|
|
CommRAM16[0x6] = FLIPENDIAN16(m_counter);
|
|
|
|
|
2021-11-05 00:23:29 +00:00
|
|
|
// we only send what we need to; helps cut down on bandwidth
|
|
|
|
// each machine has to receive back its own data (TODO: copy this data manually?)
|
|
|
|
for (int i = 0; i < m_numMachines; i++)
|
2021-04-14 01:20:45 +00:00
|
|
|
{
|
2021-11-05 00:23:29 +00:00
|
|
|
nets->Send(CommRAM + 0x100 + i * m_segmentSize, m_segmentSize);
|
2021-04-14 01:20:45 +00:00
|
|
|
auto& recv_data = netr->Receive();
|
|
|
|
if (recv_data.size() == 0)
|
|
|
|
{
|
|
|
|
// link broken - send an "empty" packet to alert other machines
|
|
|
|
nets->Send(nullptr, 0);
|
|
|
|
m_state = State::error;
|
2021-11-05 00:23:29 +00:00
|
|
|
if (m_gameType == GameType::one)
|
|
|
|
m_status1 = 0x40; // send "link broken" message to mainboard
|
2021-04-14 01:20:45 +00:00
|
|
|
break;
|
|
|
|
}
|
2021-11-05 00:23:29 +00:00
|
|
|
memcpy(CommRAM + 0x100 + (i + 1) * m_segmentSize, recv_data.data(), recv_data.size());
|
|
|
|
}
|
|
|
|
|
|
|
|
// swap CommRAM banks
|
|
|
|
if (m_commbank)
|
|
|
|
{
|
|
|
|
m_commbank = false;
|
|
|
|
CommRAM = Buffer;
|
|
|
|
externalCommRAM = Buffer + 0x10000;
|
2021-04-14 01:20:45 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2021-11-05 00:23:29 +00:00
|
|
|
m_commbank = true;
|
|
|
|
CommRAM = Buffer + 0x10000;
|
|
|
|
externalCommRAM = Buffer;
|
2021-04-14 01:20:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
case State::error:
|
|
|
|
// do nothing
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::Reset(void)
|
|
|
|
{
|
|
|
|
// if netboard was active, send an "empty" packet so the other machines don't get stuck waiting for data
|
|
|
|
if (m_state == State::ready)
|
|
|
|
{
|
|
|
|
nets->Send(nullptr, 0);
|
|
|
|
netr->Receive();
|
|
|
|
}
|
|
|
|
|
2021-10-30 23:00:49 +00:00
|
|
|
m_running = false;
|
2021-04-14 01:20:45 +00:00
|
|
|
m_state = State::start;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool CSimNetBoard::IsAttached(void)
|
|
|
|
{
|
|
|
|
return m_attached;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool CSimNetBoard::IsRunning(void)
|
|
|
|
{
|
2021-10-30 23:00:49 +00:00
|
|
|
return m_attached && m_running;
|
2021-04-14 01:20:45 +00:00
|
|
|
}
|
|
|
|
|
2022-07-11 15:43:59 +00:00
|
|
|
void CSimNetBoard::GetGame(const Game& gameInfo)
|
2021-04-14 01:20:45 +00:00
|
|
|
{
|
|
|
|
m_gameInfo = gameInfo;
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::ConnectProc(void)
|
|
|
|
{
|
|
|
|
using namespace std::chrono_literals;
|
|
|
|
|
|
|
|
if (m_connected)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printf("Connecting to %s:%i ..\n", addr_out.c_str(), port_out);
|
|
|
|
|
|
|
|
// wait until TCPSend has connected to the next machine
|
|
|
|
while (!nets->Connect())
|
|
|
|
{
|
2021-10-30 23:00:49 +00:00
|
|
|
if (m_quit)
|
2021-04-14 01:20:45 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// wait until TCPReceive has accepted a connection from the previous machine
|
|
|
|
while (!netr->Connected())
|
|
|
|
{
|
2021-10-30 23:00:49 +00:00
|
|
|
if (m_quit)
|
2021-04-14 01:20:45 +00:00
|
|
|
return;
|
|
|
|
std::this_thread::sleep_for(1ms);
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("Successfully connected.\n");
|
|
|
|
|
|
|
|
m_connected = true;
|
2021-10-30 23:00:49 +00:00
|
|
|
}
|
|
|
|
|
2021-11-05 00:23:29 +00:00
|
|
|
uint8_t CSimNetBoard::ReadCommRAM8(unsigned addr)
|
|
|
|
{
|
|
|
|
return externalCommRAM[addr];
|
|
|
|
}
|
|
|
|
|
|
|
|
uint16_t CSimNetBoard::ReadCommRAM16(unsigned addr)
|
|
|
|
{
|
|
|
|
return *(uint16_t*)&externalCommRAM[addr];
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t CSimNetBoard::ReadCommRAM32(unsigned addr)
|
|
|
|
{
|
|
|
|
return *(uint32_t*)&externalCommRAM[addr];
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::WriteCommRAM8(unsigned addr, uint8_t data)
|
|
|
|
{
|
|
|
|
externalCommRAM[addr] = data;
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::WriteCommRAM16(unsigned addr, uint16_t data)
|
|
|
|
{
|
|
|
|
*(uint16_t*)&externalCommRAM[addr] = data;
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::WriteCommRAM32(unsigned addr, uint32_t data)
|
|
|
|
{
|
|
|
|
*(uint32_t*)&externalCommRAM[addr] = data;
|
|
|
|
}
|
|
|
|
|
2021-10-30 23:00:49 +00:00
|
|
|
uint16_t CSimNetBoard::ReadIORegister(unsigned reg)
|
|
|
|
{
|
|
|
|
if (!IsRunning())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
switch (reg)
|
|
|
|
{
|
|
|
|
case 0x00:
|
|
|
|
return m_IRQ2ack;
|
|
|
|
case 0x88:
|
|
|
|
return m_status0;
|
|
|
|
case 0x8a:
|
|
|
|
return m_status1;
|
|
|
|
default:
|
|
|
|
ErrorLog("read from unknown IO register 0x%02x", reg);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void CSimNetBoard::WriteIORegister(unsigned reg, uint16_t data)
|
|
|
|
{
|
|
|
|
switch (reg)
|
|
|
|
{
|
|
|
|
case 0x00:
|
|
|
|
m_IRQ2ack = data;
|
|
|
|
break;
|
|
|
|
case 0x88:
|
|
|
|
m_status0 = data;
|
|
|
|
break;
|
|
|
|
case 0x8a:
|
|
|
|
m_status1 = data;
|
|
|
|
break;
|
|
|
|
case 0xc0:
|
|
|
|
if (data == 0)
|
|
|
|
Reset();
|
|
|
|
m_running = (data != 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ErrorLog("write to unknown IO register 0x%02x", reg);
|
|
|
|
}
|
2021-04-14 01:20:45 +00:00
|
|
|
}
|