Xargon/Duckstation
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2558 commits 1 branch 1 tag 100 MiB
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15 commits

Author SHA1 Message Date
Connor McLaughlin 0fca011bd4 CPU/Recompiler: Fix OOB in register pairing 2020-10-19 02:23:04 +10:00
Connor McLaughlin a6f8dde790 CPU/Recompiler: Faster ASM dispatcher 2020-10-18 14:54:38 +10:00
Connor McLaughlin 60eb22537b CPU/Recompiler: Flush caller-saved regs before calling functions 
Should provide a very small performance boost.
 2020-08-23 14:03:10 +10:00
Connor McLaughlin 901ca71fdc CPU/Recompiler: Add temporary inhibiting of register allocation 2020-08-08 23:44:13 +10:00
Connor McLaughlin 71c1e243fe Remove YBaseLib dependency 2020-01-10 13:40:53 +10:00
Connor McLaughlin 29355bc44d CPU/Recompiler: Move branch codegen to base class 2019-12-27 20:38:07 +10:00
Connor McLaughlin 44c76f3bf3 CPU/Recompiler: Support three-operand basic operations 
e.g. add r1, r2, r3. This eliminates the extra move on ARM.
 2019-12-13 00:51:41 +10:00
Connor McLaughlin 20c7aaf74b CPU/Recompiler: Support pushing/popping the register cache state 2019-12-12 20:15:54 +10:00
Connor McLaughlin e518cbfffb CPU/Recompiler: Fallback-all-instructions working in AArch64 2019-12-03 20:45:14 +10:00
Connor McLaughlin 8c5fcc8f48 CPU: Fix more load delay slot issues 
Fixes Spyro again. b{ltz,gez}(al)? disabled in the recompiler until
issues are fixed.
 2019-11-24 01:11:51 +10:00
Connor McLaughlin f14ad1d3c4 CPU/Recompiler: Implement add/addu/addi 2019-11-23 00:26:56 +10:00
Connor McLaughlin 167e2a3454 CPU/Recompiler: Implement j/jal/jr/jalr/beq/bne/bgtz/blez 2019-11-22 21:41:10 +10:00
Connor McLaughlin 7aafaeacbc CPU/Recompiler: Implement lb/lbu/lh/lhu/lw/sb/sh/sw instructions 
Currently not passing CPU tests when combined with lwl/lwr.
 2019-11-21 23:34:04 +10:00
Connor McLaughlin 5217088d82 CPU: Refactor load delay handling 
Now works when mixing interpreter and recompiler code.
 2019-11-20 00:15:15 +10:00
Connor McLaughlin 1d6c4a3af1 CPU: Basic recompiler implementation for x64 (lui, ori, addiu) 
Disabled by default.
 2019-11-19 20:38:05 +10:00