Xargon/Duckstation
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Author SHA1 Message Date
Connor McLaughlin 77fe883901 System: Default to NTSC region for BIOS boot if auto 2019-11-16 20:52:39 +10:00
Connor McLaughlin b57f1d4a60 HostInterface: Implement non-vsync based speed throttler 
Needed for PAL games.
 2019-11-16 20:52:39 +10:00
Connor McLaughlin 246c97ccb3 System: Scaffolding for multi-system/multi-bios 2019-11-16 20:50:59 +10:00
Connor McLaughlin d6209937fb CDROM: Properly handle audio sectors in SeekL 2019-11-16 12:54:41 +10:00
Connor McLaughlin f12b97e98b DMA: Add missing transfer_ticks to save state 2019-11-16 01:51:22 +10:00
Connor McLaughlin 4524172573 Frontend: Use flip model swap chains in D3D 2019-11-16 01:45:31 +10:00
Connor McLaughlin 2399c1dab7 SPU: Fix incorrect step value in attack phase 2019-11-16 01:43:34 +10:00
Connor McLaughlin a47492382c System: Add "fast boot" option (skip boot logo) 2019-11-16 01:04:52 +10:00
Connor McLaughlin 30fd7a6683 DMA: Support delaying transfers 
Fixes Syphon Filter 2/3.
 2019-11-15 23:27:56 +10:00
Connor McLaughlin e02ebb1b2a SPU: Mute voice without release phase on loop/end flag 
Fixes channels getting stuck in Syphon Filter.
 2019-11-15 17:24:11 +10:00
Connor McLaughlin 5b5d22fd27 SPU: Stub out transfer control register 
Fixes sound in Ridge Racer.
 2019-11-15 16:44:23 +10:00
Connor McLaughlin d9c27c4ee3 SPU: Fix sustain step being ignored 2019-11-15 16:42:25 +10:00
Connor McLaughlin 4e9d5b77f8 GPU: Fix swapped bytes for VRAM->CPU transfers 2019-11-15 15:05:27 +10:00
Connor McLaughlin f27ad2fa67 Frontend: Re-implement fullscreen 2019-11-15 14:57:27 +10:00
Connor McLaughlin a25fe54a4b Frontend: Swap L1/R1 and L2/R2 bindings 2019-11-15 14:13:05 +10:00
Connor McLaughlin 708ce25cb0 GPU/HW: Fix resolution changing while running corrupting screen 2019-11-14 22:24:47 +10:00
Connor McLaughlin 49569d29aa GPU: Refactor command execution/VRAM->CPU transfers 
Simpler, and handles odd sizes correctly.
 2019-11-14 22:17:11 +10:00
Connor McLaughlin bc9ed3572b GPU/HW: Fix flipped GPU readback in D3D11 2019-11-14 22:11:12 +10:00
Connor McLaughlin 9d66638bce GPU: Handle oversized transfers (wrap around behavior) 2019-11-14 20:31:48 +10:00
Connor McLaughlin 9ea7a8418c GPU: Eliminate temporary buffer when reading back 2019-11-14 17:17:22 +10:00
Connor McLaughlin 3998b9684e GPU/HW: GPU-based RGBA8->RGB5551 conversion for readbacks 2019-11-14 17:16:21 +10:00
Connor McLaughlin 878a76e258 Common: Fix issues in utility classes for readbacks 2019-11-14 16:57:58 +10:00
Connor McLaughlin 4bab3bffc0 Frontend: Fix display linear filtering setting not applying 2019-11-14 01:22:35 +10:00
Connor McLaughlin 53881219ce GPU: Fix handling of interlaced non-480-line mode 2019-11-14 00:59:09 +10:00
Connor McLaughlin 7152d54104 GPU: Simplify 480i mode handling in CRTC 2019-11-14 00:58:15 +10:00
Connor McLaughlin b48accf0bf GPU/HW: Fix 24-bit output broken with >1x res scale 2019-11-13 22:54:52 +10:00
Connor McLaughlin 76172c88f3 GPU/HW: Disable blending when updating VRAM 
Fixes random breakage when it was previously enabled.
 2019-11-13 22:48:39 +10:00
Connor McLaughlin f7f4818de4 GPU/HW: Explicitly specify std140 layout for UBOs 2019-11-13 22:48:14 +10:00
Connor McLaughlin 8cfb8d7922 CDROM: Fix track skip behavior with track=0 
Fixes Doom.
 2019-11-13 16:33:51 +10:00
Connor McLaughlin 525bbf48d7 CDImage: Set data bit in Q subchannel for bin images 2019-11-13 16:28:43 +10:00
Connor McLaughlin 8e06f86db8 CDROM: Implement auto-pause at end of track 2019-11-12 20:40:37 +10:00
Connor McLaughlin 85413218cb SPU: Check upper 8 byte block of ADPCM block for interrupt 
Fixes NFS2 stuck after selecting Race.
 2019-11-12 18:56:55 +10:00
Connor McLaughlin 90cf6b8b41 CDROM: Don't lose INT1 interrupts from command execution 2019-11-12 18:02:36 +10:00
Connor McLaughlin 6a82333d8f Pad: Only buffer a single byte 
Fixes Croc 2 memory card access freezing.
 2019-11-12 01:32:06 +10:00
Connor McLaughlin d8452d7d7d GPU: Track horizontal blanking, correct timer increment point 2019-11-12 01:32:06 +10:00
Connor McLaughlin f3baee2582 DMA: Hack for self-referencing DMA loops 
I need to figure how these are being generated in the first place.
 2019-11-11 20:37:13 +10:00
Connor McLaughlin 29674df803 DMA: Simplify address masking 2019-11-11 20:34:41 +10:00
Connor McLaughlin 6f4cf7d5e3 System: Support changing BIOS path 2019-11-11 19:43:39 +10:00
Connor McLaughlin 7b6a2f1aaf Build: Fix CMake build 2019-11-11 14:34:46 +10:00
Connor McLaughlin 99c264947d SPU: Implement capture buffers 
Fixes Crash Team Racing and lipsyncing within.
 2019-11-11 14:06:30 +10:00
Connor McLaughlin 26437e31dd SPU: Fire interrupt on DMA reads/writes too 2019-11-11 14:05:58 +10:00
Connor McLaughlin 8722757412 SPU: Implement pitch modulation 2019-11-11 00:41:09 +10:00
Connor McLaughlin 5a84122862 CDROM: Implement CDDA report 2019-11-10 23:03:52 +10:00
Connor McLaughlin ab90d287bb CDROM: Use Sub-Channel Q for GetLocP 2019-11-10 22:45:48 +10:00
Connor McLaughlin 6bb4f8e728 CDImage: Support generating Q Sub-Channel 2019-11-10 22:44:53 +10:00
Connor McLaughlin 2cc5084dd1 CDImage: Handle cue sheets where pregap is in file 2019-11-10 15:16:48 +10:00
Connor McLaughlin 68fe492130 CDROM: Use seek time formula from Mednafen 2019-11-10 15:01:18 +10:00
Connor McLaughlin c0208b6e78 GPU: Flush render before changing drawing area/offset 
Fixes "random" broken polygons in hardware backends.
 2019-11-09 22:56:53 +10:00
Connor McLaughlin dbc22fe841 GPU/HW: Fix typo preventing fragment shader based VRAM writes from being used 2019-11-09 21:36:37 +10:00
Connor McLaughlin 5dd4f6f65e CDROM: Implement ReadTOC command 2019-11-09 00:21:11 +10:00