Connor McLaughlin
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74d51c80fc
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CPU: Implement TAR COP0 register
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2019-10-04 02:48:19 +10:00 |
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Connor McLaughlin
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eddd2c1990
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CPU: Correct bits for CAUSE.CE, EPC for fetch
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2019-10-04 02:27:34 +10:00 |
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Connor McLaughlin
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1f6130f04a
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CPU: Restore faster IPS
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2019-10-03 16:45:54 +10:00 |
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Connor McLaughlin
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8b4ec87055
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CPU: Support printing instruction operands when tracing
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2019-09-30 17:32:58 +10:00 |
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Connor McLaughlin
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71022e9cca
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Implement memory cards
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2019-09-30 01:07:38 +10:00 |
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Connor McLaughlin
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d3893bc9f2
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CPU: Make it run a bit faster, but needs proper timings
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2019-09-28 01:43:10 +10:00 |
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Connor McLaughlin
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a479d820d4
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CPU: Delay interrupts if the instruction in the pipeline is a TE instruction
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2019-09-27 23:43:52 +10:00 |
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Connor McLaughlin
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9359d0778e
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Clean up memory access handlers, reduce template specializations
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2019-09-25 00:36:24 +10:00 |
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Connor McLaughlin
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4aca52cdf4
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CPU: Silence some debug spam
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2019-09-24 23:56:30 +10:00 |
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Connor McLaughlin
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948ac50020
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CPU: Refactoring, implement LWC/SWC
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2019-09-22 02:06:47 +10:00 |
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Connor McLaughlin
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c988af453c
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Refactor timing to allow sync/updates in the middle of a slice
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2019-09-21 01:24:33 +10:00 |
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Connor McLaughlin
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ad652c47ed
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Basic CD image loading
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2019-09-20 20:14:00 +10:00 |
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Connor McLaughlin
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a84b3d7a2b
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CPU: Fix interrupts in branch delay slots messing up PC
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2019-09-18 00:22:17 +10:00 |
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Connor McLaughlin
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4025d6e4a6
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GTE: Stub and register read/write function
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2019-09-17 23:38:04 +10:00 |
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Connor McLaughlin
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e3c6035152
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CDROM: Implement get version and getstat commands
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2019-09-17 22:18:58 +10:00 |
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Connor McLaughlin
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2128a2984b
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Add interrupt controller emulation
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2019-09-17 16:26:00 +10:00 |
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Connor McLaughlin
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f47688b61f
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System: Basic timings for GPU scanout
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2019-09-17 14:25:25 +10:00 |
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Connor McLaughlin
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540f282213
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CPU: Fix incorrect exception vector for break
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2019-09-15 12:43:54 +10:00 |
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Connor McLaughlin
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d58dbe04c0
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CPU: Fix load delay register reads for same register in delay slot
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2019-09-15 12:16:51 +10:00 |
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Connor McLaughlin
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4ca3b4b570
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CPU: Fix alignment exception on register indirect branch
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2019-09-15 01:13:11 +10:00 |
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Connor McLaughlin
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bea727bbe4
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CPU: Fix BGEZAL with rs == ra
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2019-09-15 01:02:35 +10:00 |
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Connor McLaughlin
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2560efbebd
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Save state support
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2019-09-14 20:28:47 +10:00 |
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Connor McLaughlin
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f47d44c151
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CPU: Implement break instruction
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2019-09-14 14:41:41 +10:00 |
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Connor McLaughlin
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32a36ef1bc
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CPU: Implement alignment (memory) exception
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2019-09-14 14:29:23 +10:00 |
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Connor McLaughlin
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ced3038e73
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CPU: Implement sub instruction
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2019-09-14 13:39:36 +10:00 |
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Connor McLaughlin
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1afa02d475
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CPU: Fix overflowed register written back in add instruction
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2019-09-14 13:33:29 +10:00 |
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Connor McLaughlin
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459db392e7
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CPU: Add missing cop0 register reads
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2019-09-14 13:31:44 +10:00 |
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Connor McLaughlin
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9f36384752
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System: Support sideloading EXE files via BIOS patch
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2019-09-14 13:22:34 +10:00 |
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Connor McLaughlin
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27913cd20a
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Partial implementation of DMA controller and GPU stubs
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2019-09-11 14:01:19 +10:00 |
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Connor McLaughlin
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2149ab4d69
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Initial commit
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2019-09-11 14:00:42 +10:00 |
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