Xargon/Duckstation
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141 commits 1 branch 1 tag 100 MiB
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30 commits

Author SHA1 Message Date
Connor McLaughlin 74d51c80fc CPU: Implement TAR COP0 register 2019-10-04 02:48:19 +10:00
Connor McLaughlin eddd2c1990 CPU: Correct bits for CAUSE.CE, EPC for fetch 2019-10-04 02:27:34 +10:00
Connor McLaughlin 1f6130f04a CPU: Restore faster IPS 2019-10-03 16:45:54 +10:00
Connor McLaughlin 8b4ec87055 CPU: Support printing instruction operands when tracing 2019-09-30 17:32:58 +10:00
Connor McLaughlin 71022e9cca Implement memory cards 2019-09-30 01:07:38 +10:00
Connor McLaughlin d3893bc9f2 CPU: Make it run a bit faster, but needs proper timings 2019-09-28 01:43:10 +10:00
Connor McLaughlin a479d820d4 CPU: Delay interrupts if the instruction in the pipeline is a TE instruction 2019-09-27 23:43:52 +10:00
Connor McLaughlin 9359d0778e Clean up memory access handlers, reduce template specializations 2019-09-25 00:36:24 +10:00
Connor McLaughlin 4aca52cdf4 CPU: Silence some debug spam 2019-09-24 23:56:30 +10:00
Connor McLaughlin 948ac50020 CPU: Refactoring, implement LWC/SWC 2019-09-22 02:06:47 +10:00
Connor McLaughlin c988af453c Refactor timing to allow sync/updates in the middle of a slice 2019-09-21 01:24:33 +10:00
Connor McLaughlin ad652c47ed Basic CD image loading 2019-09-20 20:14:00 +10:00
Connor McLaughlin a84b3d7a2b CPU: Fix interrupts in branch delay slots messing up PC 2019-09-18 00:22:17 +10:00
Connor McLaughlin 4025d6e4a6 GTE: Stub and register read/write function 2019-09-17 23:38:04 +10:00
Connor McLaughlin e3c6035152 CDROM: Implement get version and getstat commands 2019-09-17 22:18:58 +10:00
Connor McLaughlin 2128a2984b Add interrupt controller emulation 2019-09-17 16:26:00 +10:00
Connor McLaughlin f47688b61f System: Basic timings for GPU scanout 2019-09-17 14:25:25 +10:00
Connor McLaughlin 540f282213 CPU: Fix incorrect exception vector for break 2019-09-15 12:43:54 +10:00
Connor McLaughlin d58dbe04c0 CPU: Fix load delay register reads for same register in delay slot 2019-09-15 12:16:51 +10:00
Connor McLaughlin 4ca3b4b570 CPU: Fix alignment exception on register indirect branch 2019-09-15 01:13:11 +10:00
Connor McLaughlin bea727bbe4 CPU: Fix BGEZAL with rs == ra 2019-09-15 01:02:35 +10:00
Connor McLaughlin 2560efbebd Save state support 2019-09-14 20:28:47 +10:00
Connor McLaughlin f47d44c151 CPU: Implement break instruction 2019-09-14 14:41:41 +10:00
Connor McLaughlin 32a36ef1bc CPU: Implement alignment (memory) exception 2019-09-14 14:29:23 +10:00
Connor McLaughlin ced3038e73 CPU: Implement sub instruction 2019-09-14 13:39:36 +10:00
Connor McLaughlin 1afa02d475 CPU: Fix overflowed register written back in add instruction 2019-09-14 13:33:29 +10:00
Connor McLaughlin 459db392e7 CPU: Add missing cop0 register reads 2019-09-14 13:31:44 +10:00
Connor McLaughlin 9f36384752 System: Support sideloading EXE files via BIOS patch 2019-09-14 13:22:34 +10:00
Connor McLaughlin 27913cd20a Partial implementation of DMA controller and GPU stubs 2019-09-11 14:01:19 +10:00
Connor McLaughlin 2149ab4d69 Initial commit 2019-09-11 14:00:42 +10:00