Xargon/Duckstation
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99 commits

Author SHA1 Message Date
Stenzek 312790c9a6
CPU/NewRec: Handle mtc0 rt, sr 2023-11-10 21:19:45 +10:00
Stenzek 3dfc3bd2ba
CPU: Fix incorrect scratchpad masking 2023-11-06 18:09:27 +10:00
Stenzek 9501439d6b
CPU: Add new experimental recompiler 2023-10-18 00:49:01 +10:00
Stenzek 9d40164f84
CPU/Recompiler: Offset LUT fastmem pointers 2023-10-18 00:49:01 +10:00
Stenzek a062b00c1a
Bus: Protect main RAM buffer 
Get rid of write-time checks.
 2023-10-18 00:49:01 +10:00
Stenzek 79e1ae3e54
CPU/CodeCache: Rewrite using new-rec's block management 2023-10-18 00:49:01 +10:00
Stenzek f9d8a49324
CPU: Fix incorrect writing of unaligned words via cheats 2023-10-11 01:10:31 +10:00
Stenzek 56fc207af6 CPU: Use lookup tables for memory access 2023-10-01 20:48:02 +10:00
Stenzek 05fe925409 CPU: Make namespacing explicit 2023-10-01 20:48:02 +10:00
Stenzek ac0601f408 Common: Drop String, add SmallString 2023-09-23 14:14:52 +10:00
Stenzek 60aca2fc4d Misc: Swap LIKELY/UNLIKELY macros for attributes 2023-09-05 22:10:50 +10:00
Stenzek a4c7293d28 CPU: Fix breakpoints/single stepping 2023-09-03 19:49:34 +10:00
Stenzek 80e3d29ab8 Misc: clang-cl warning clean-up 2023-09-03 14:30:26 +10:00
Stenzek 199c53f3af BIOS: Replace TTY patch with syscall hook 2023-08-30 00:44:01 +10:00
Stenzek 92b1c21b8a CPU: Fix crash on breakpoint add/trace enable 2023-08-30 00:44:01 +10:00
Stenzek e57ad0b6aa Host: Backport translations cache 
Note: You'll need a new command line for lupdate.

..\..\..\dep\msvc\qt\6.5.0\msvc2022_64\bin\lupdate.exe ../ ../../core/ ../../util/ -tr-function-alias QT_TRANSLATE_NOOP+=TRANSLATE,QT_TRANSLATE_NOOP+=TRANSLATE_SV,QT_TRANSLATE_NOOP+=TRANSLATE_STR,QT_TRANSLATE_NOOP+=TRANSLATE_FS,QT_TRANSLATE_N_NOOP3+=TRANSLATE_FMT,QT_TRANSLATE_NOOP+=TRANSLATE_NOOP -ts duckstation-qt_LANGUAGE.ts
 2023-08-20 12:40:47 +10:00
Stenzek 5b980dafa5 System: Refactor main loop 
Reduces JIT exits.
Improves runahead performance.
 2023-08-16 01:13:00 +10:00
Stenzek 84e5fbe0c6 CPU: HLE implementation of PCDrv (host file access) 2023-04-29 20:45:39 +10:00
Connor McLaughlin fe08d34e52 Qt: Add COP0/GTE registers to debugger list 2023-01-15 15:13:54 +10:00
Connor McLaughlin 8c7a192128 Misc: Add copyright/license statement to applicable files 
Should've did this in the beginning.
 2022-12-04 21:03:49 +10:00
Connor McLaughlin b42b5501f6 UI: Massive revamp, new features and improvements 2022-07-22 21:19:54 +10:00
Connor McLaughlin b7fbde31a7 Move utility classes from common to own static lib 2022-07-21 17:29:58 +10:00
Connor McLaughlin 46737acecd CPU: Prevent mismatched va_start/va_end in log 2022-01-06 22:47:10 +10:00
Connor McLaughlin bbf67ef544 CPU: Warning fix 2021-12-25 14:28:32 +10:00
Connor McLaughlin 53299e3c7b CPU/Interpreter: Load delay check should be a debug assertion 2021-07-24 13:04:54 +10:00
Connor McLaughlin 30db081a64 CPU: Simulate stalls from GTE instructions 2021-07-16 12:27:31 +10:00
Connor McLaughlin 4f09d61825 CPU: Don't panic on invalid instructions 2021-06-15 22:58:29 +10:00
Connor McLaughlin 1ed1d641a6 CPU/Recompiler: Don't use intepreter icache when falling back 
Fixes broken rendering in TOCA 2.

It has self-modifying code every frame, which gets falled back to the
interpreter, and using the interpreter's icache, which resulted in
stale code executing.
 2021-05-20 12:19:23 +10:00
Connor McLaughlin e382df0d41 Support expanding RAM to 8MB (dev console) 2021-05-03 12:43:33 +10:00
Connor McLaughlin f1310bf93a System: Don't discard PGXP state when runahead-rollbacking 
You'll still see some glitches if you have the frame count set too high,
since you'll get imprecise values for any vertices which have moved, but
that's going to happen anyway because of the runahead in the first
place.
 2021-04-28 02:51:44 +10:00
Connor McLaughlin 40731b49fc Bus: Handle CPU-internal narrow writes 
The full 32-bits of the GPR are used.

Fixes SoundScope in the BIOS Shell.
 2021-04-26 22:08:18 +10:00
Connor McLaughlin 3106c797d9 CPU: Reduce severity of some log statements 2021-04-19 15:19:08 +10:00
Connor McLaughlin 442b801d39 CPU: Implement cop0 execution and data breakpoints 2021-04-14 19:06:52 +10:00
Connor McLaughlin 22fdd80cc3 CPU/Interpreter: Out of range cop0 reads should be nops 2021-04-14 19:06:52 +10:00
Connor McLaughlin dd5277321b CPU/CachedInterpreter: Fix infinite loop when block compile fails 2021-04-14 19:06:52 +10:00
Connor McLaughlin e087e6f3a2 CPU/Recompiler: Prevent using fastmem when cache is isolated 
No point even trying since it's just going to fault.
 2021-04-12 02:08:56 +10:00
Connor McLaughlin 922d320523 CPU/Recompiler: Reserve whole fastmem region to avoid clashes 2021-04-11 12:42:51 +10:00
Connor McLaughlin 209827b67c PGXP: Compute PSX values on demand for CPU instructions 
Generates shorter code for the recompiler.
 2021-02-18 02:08:48 +10:00
Connor McLaughlin 1b881fc60b PGXP: Combine instr and rtVal parameters for CPU_LUI 2021-02-18 02:08:47 +10:00
Connor McLaughlin 0bfa1bf873 PGXP: Fix MFC0/MTC0 
Doubt it'll change anything.
 2021-02-18 02:08:47 +10:00
Connor McLaughlin a722fd6b53 PGXP: Make mult/div compute results instead of parameters 
Lets us call it from the recompiler.
 2021-02-18 02:08:47 +10:00
Connor McLaughlin 33a5617ea3 PGXP: Remove some unused parameter from M{F,T}{HI,LO} 2021-02-18 02:08:47 +10:00
Connor McLaughlin efecb44344 PGXP: Combine a couple of instructions 2021-02-18 02:08:47 +10:00
Connor McLaughlin 9d80c48d6f CPU: Fix icache missing from save state 2021-01-31 16:39:51 +10:00
Connor McLaughlin e3262fc0a4 CPU: Compile fix for debug builds 2021-01-05 00:46:41 +10:00
Connor McLaughlin 9ff8130e40 fixup! CPU: Make trace-to-file toggleable at runtime and in release builds 2021-01-04 03:11:14 +10:00
Connor McLaughlin bf1d51b5d8 CPU: Make trace-to-file toggleable at runtime and in release builds 2021-01-04 03:11:14 +10:00
Connor McLaughlin c9240eea72 CPU/Recompiler: Use PGXP interpreter for fallback 
Fixes holes in geometry with PGXP enabled in Threads of Fate.
 2021-01-01 17:16:55 +10:00
Connor McLaughlin 3b23542ec9 CPU: Provide debugger/breakpoint/step functionality 2020-12-17 11:57:47 +10:00
Connor McLaughlin bf2e38aed5 CPU/Recompiler: Implement LUT-based fastmem 2020-11-24 14:49:21 +10:00