Xargon/Duckstation
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45 commits

Author SHA1 Message Date
Stenzek 3fd86a69a4
CPU/PGXP: Use component enum 2024-05-18 00:33:22 +10:00
Stenzek 29d4e04e3b
CPU/PGXP: Use bit math for flags instead of union 2024-05-17 23:46:18 +10:00
Stenzek 295081fe62
Misc: Replace offsetof with constexpr-friendly OFFSETOF 
Fixes build with clang-18.
 2024-04-28 15:25:24 +10:00
Stenzek 35f0d7f623
CPU: Update debug dispatcher flag on init 2024-04-22 00:08:16 +10:00
Stenzek fa6850902a
CPU: Make interrupts actually edge-triggered 2024-03-18 01:46:19 +10:00
Stenzek 71094a0e44
CPU: Implement memory breakpoints/watchpoints 2024-02-28 00:02:02 +10:00
Stenzek ef4389cea8
Qt: Cache CPU register values 
That way they don't update while running.
 2024-02-27 22:38:43 +10:00
Stenzek eeef0a92bb
CPU: Make single step go through the "normal" execution path 
That way it exits and re-enters the dynarec as expected.
 2024-02-27 21:04:25 +10:00
Stenzek 35cdfc5ef7
CPU: Move PGXP registers earlier in struct 2024-02-24 14:57:31 +10:00
Stenzek bc2c334370
Misc: Combine some redundant functions 2023-12-13 20:56:40 +10:00
Stenzek 185af2b039
CPU/NewRec: Fix lui/mfc0 not getting called in CPU PGXP mode 2023-12-06 20:12:20 +10:00
Stenzek 3dfc3bd2ba
CPU: Fix incorrect scratchpad masking 2023-11-06 18:09:27 +10:00
Stenzek 56fc207af6 CPU: Use lookup tables for memory access 2023-10-01 20:48:02 +10:00
Stenzek 5b980dafa5 System: Refactor main loop 
Reduces JIT exits.
Improves runahead performance.
 2023-08-16 01:13:00 +10:00
Stenzek 84e5fbe0c6 CPU: HLE implementation of PCDrv (host file access) 2023-04-29 20:45:39 +10:00
Connor McLaughlin fe08d34e52 Qt: Add COP0/GTE registers to debugger list 2023-01-15 15:13:54 +10:00
Connor McLaughlin 8c7a192128 Misc: Add copyright/license statement to applicable files 
Should've did this in the beginning.
 2022-12-04 21:03:49 +10:00
Connor McLaughlin 8dcd68b0a8 CPU: Make Safe{Read,Write}Memory{Byte,Halfword,Word} truely safe 2021-09-10 15:53:14 +10:00
Connor McLaughlin 30db081a64 CPU: Simulate stalls from GTE instructions 2021-07-16 12:27:31 +10:00
Connor McLaughlin acda42be16 CPU/Recompiler: Get rid of non-constant offsetofs 2021-05-20 12:19:24 +10:00
Connor McLaughlin e087e6f3a2 CPU/Recompiler: Prevent using fastmem when cache is isolated 
No point even trying since it's just going to fault.
 2021-04-12 02:08:56 +10:00
C.W. Betts fb7a8886f1 Add more printflike macros. 2021-03-29 13:56:19 -06:00
Connor McLaughlin e3262fc0a4 CPU: Compile fix for debug builds 2021-01-05 00:46:41 +10:00
Connor McLaughlin bf1d51b5d8 CPU: Make trace-to-file toggleable at runtime and in release builds 2021-01-04 03:11:14 +10:00
Connor McLaughlin 3b23542ec9 CPU: Provide debugger/breakpoint/step functionality 2020-12-17 11:57:47 +10:00
Connor McLaughlin be63d893cd CPU: Use partial icache fills for non-line-aligned addresses 2020-10-30 00:44:40 +10:00
Connor McLaughlin 7566c45f64 CPU/Recompiler: Implement fastmem 2020-10-18 14:54:38 +10:00
Connor McLaughlin 27697d0508 System: Implement CPU overclocking [SAVEVERSION+] 
Partial credit to @CookiePLMonster as well.
 2020-09-30 23:48:34 +10:00
Connor McLaughlin 19d6037b99 CPU: Implement instruction cache simulation 
Implemented for all execution modes. Disabled by default in the cached
interpreter and recompiler, always enabled in the pure interpreter.
 2020-08-29 22:07:40 +10:00
Connor McLaughlin 1d5f810a4b CPU/Recompiler: Disable memory access exceptions by default 
This means it'll no longer pass amidog's CPU test in the default config.
But no games rely on this. You can enable it in advanced options if you
want to pass the CPU test.
 2020-08-08 23:44:13 +10:00
Connor McLaughlin b6f871d2b9
JIT optimizations and refactoring (#675) 
* CPU/Recompiler: Use rel32 call where possible for no-args

* JitCodeBuffer: Support using preallocated buffer

* CPU/Recompiler/AArch64: Use bl instead of blr for short branches

* CPU/CodeCache: Allocate recompiler buffer in program space

This means we don't need 64-bit moves for every call out of the
recompiler.

* GTE: Don't store as u16 and load as u32

* CPU/Recompiler: Add methods to emit global load/stores

* GTE: Convert class to namespace

* CPU/Recompiler: Call GTE functions directly

* Settings: Turn into a global variable

* GPU: Replace local pointers with global

* InterruptController: Turn into a global pointer

* System: Replace local pointers with global

* Timers: Turn into a global instance

* DMA: Turn into a global instance

* SPU: Turn into a global instance

* CDROM: Turn into a global instance

* MDEC: Turn into a global instance

* Pad: Turn into a global instance

* SIO: Turn into a global instance

* CDROM: Move audio FIFO to the heap

* CPU/Recompiler: Drop ASMFunctions

No longer needed since we have code in the same 4GB window.

* CPUCodeCache: Turn class into namespace

* Bus: Local pointer -> global pointers

* CPU: Turn class into namespace

* Bus: Turn into namespace

* GTE: Store registers in CPU state struct

Allows relative addressing on ARM.

* CPU/Recompiler: Align code storage to page size

* CPU/Recompiler: Fix relative branches on A64

* HostInterface: Local references to global

* System: Turn into a namespace, move events out

* Add guard pages

* Android: Fix build
 2020-07-31 17:09:18 +10:00
Connor McLaughlin 5c1c467e38 GTE: Add widescreen hack 2020-07-18 00:28:37 +10:00
Connor McLaughlin 2d74062abb CPU: Delay interrupts by one instruction/block 
Fixes Gameshark Sampler Disc.
 2020-07-03 01:51:08 +10:00
Connor McLaughlin 1b9609ef61 Implement event-based scheduler instead of lock-step components 2020-01-24 16:23:39 +10:00
Connor McLaughlin 9fa8eb239e CPU: Force-inline some accessor functions 2019-12-05 23:02:03 +10:00
Connor McLaughlin eeea5125f7 CPU: Use pending ticks as downcount comparison 
Saves a few cycles decrementing the downcount.
 2019-12-05 16:28:46 +10:00
Connor McLaughlin 8c5fcc8f48 CPU: Fix more load delay slot issues 
Fixes Spyro again. b{ltz,gez}(al)? disabled in the recompiler until
issues are fixed.
 2019-11-24 01:11:51 +10:00
Connor McLaughlin 7aafaeacbc CPU/Recompiler: Implement lb/lbu/lh/lhu/lw/sb/sh/sw instructions 
Currently not passing CPU tests when combined with lwl/lwr.
 2019-11-21 23:34:04 +10:00
Connor McLaughlin 5217088d82 CPU: Refactor load delay handling 
Now works when mixing interpreter and recompiler code.
 2019-11-20 00:15:15 +10:00
Connor McLaughlin 1d6c4a3af1 CPU: Basic recompiler implementation for x64 (lui, ori, addiu) 
Disabled by default.
 2019-11-19 20:38:05 +10:00
Connor McLaughlin 6f4cf7d5e3 System: Support changing BIOS path 2019-11-11 19:43:39 +10:00
Connor McLaughlin 4a6f283484 CPU: Add trace log to file support 2019-11-04 00:55:07 +10:00
Connor McLaughlin 9d5f3c1306 CPU: Support stalling CPU for bus activity such as DMA 2019-10-18 00:20:38 +10:00
Connor McLaughlin 4422fb0545 CPU: Memory access timings 2019-10-04 20:30:54 +10:00
Connor McLaughlin bddbab9d60 Rename to DuckStation 2019-10-04 13:54:09 +10:00
Renamed from src/pse/cpu_core.h (Browse further)