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Author SHA1 Message Date
Connor McLaughlin 4bb8fb211d DMA: Delay transfer/interrupt 2019-09-24 21:39:13 +10:00
Connor McLaughlin 4cc83e2228 DMA: Implement interrupts 2019-09-24 19:43:10 +10:00
Connor McLaughlin db777fdabb CDROM: Various fixes 2019-09-24 01:33:18 +10:00
Connor McLaughlin 1f13c4ad2c Pad: Fix long transmit delay breaking other things 2019-09-24 01:31:17 +10:00
Connor McLaughlin d65c9b3592 CDROM: Read timing and demute command, seek on ReadN 2019-09-23 23:31:51 +10:00
Connor McLaughlin 20f14688ca System: Support loading expansion ROMs 2019-09-23 01:38:21 +10:00
Connor McLaughlin 5d1c12c9ad Pad: Fix timing issues w/ BIOS 2019-09-23 01:25:58 +10:00
Connor McLaughlin 734d1a7ee1 InterruptController: Masked interrupts are still set in the status register 2019-09-23 01:24:36 +10:00
Connor McLaughlin fbd7fcec48 GTE: Implement NCDS (but incorrectly) 2019-09-22 21:41:11 +10:00
Connor McLaughlin f2d62fcce0 CDROM: Hack timings to get further with booting 2019-09-22 21:40:44 +10:00
Connor McLaughlin c772047715 GTE: Add AVSZ3/AVSZ4 2019-09-22 20:38:11 +10:00
Connor McLaughlin 005b06ae0c GTE: More implementation work, Reg+NCLIP+STR tests passing 2019-09-22 17:33:11 +10:00
Connor McLaughlin 3fb08a72a4 CDROM: Hack around missing pregap in images 2019-09-22 02:32:45 +10:00
Connor McLaughlin 948ac50020 CPU: Refactoring, implement LWC/SWC 2019-09-22 02:06:47 +10:00
Connor McLaughlin 2875a22987 CDROM: Reads appear to be functioning 2019-09-22 01:12:16 +10:00
Connor McLaughlin c988af453c Refactor timing to allow sync/updates in the middle of a slice 2019-09-21 01:24:33 +10:00
Connor McLaughlin ad316162f3 Basic timer implementation 2019-09-20 23:40:19 +10:00
Connor McLaughlin ad652c47ed Basic CD image loading 2019-09-20 20:14:00 +10:00
Connor McLaughlin 53e755aa68 Pad: Save state support 2019-09-20 19:21:45 +10:00
Connor McLaughlin 8cd75a4937 PAD: Basic support for digital controllers 2019-09-20 16:47:41 +10:00
Connor McLaughlin d84bffead1 GPU: Implement transparency mode 2019-09-19 00:55:06 +10:00
Connor McLaughlin 23ef1cafbd GPU: Force 16-bit precision when filling VRAM, clear mask bit 2019-09-18 15:54:57 +10:00
Connor McLaughlin d8150c996b GPU: Support dumping copies out to file 2019-09-18 15:43:25 +10:00
Connor McLaughlin e40ac7cee1 dep: Add stb_image_write 2019-09-18 15:43:03 +10:00
Connor McLaughlin 4d624946d6 GPU: Texpage attribute can change texture mode too 2019-09-18 15:24:29 +10:00
Connor McLaughlin 4d4ab898c0 GPU: Flush rendering before VRAM->VRAM copies 2019-09-18 15:15:03 +10:00
Connor McLaughlin 2c07db6dd5 GPU: Flush rendering before VRAM reads 2019-09-18 15:14:31 +10:00
Connor McLaughlin 4d38213f23 GPU: Implement VRAM-to-VRAM copies 2019-09-18 00:58:30 +10:00
Connor McLaughlin ff83f15abe dep: Add missing file 2019-09-18 00:30:26 +10:00
Connor McLaughlin 0a8bce8936 GPU: Hook up vblank interrupt 2019-09-18 00:22:41 +10:00
Connor McLaughlin a84b3d7a2b CPU: Fix interrupts in branch delay slots messing up PC 2019-09-18 00:22:17 +10:00
Connor McLaughlin 4025d6e4a6 GTE: Stub and register read/write function 2019-09-17 23:38:04 +10:00
Connor McLaughlin 6df8d42480 CDROM: Add missing fields to save state 2019-09-17 23:04:00 +10:00
Connor McLaughlin e3c6035152 CDROM: Implement get version and getstat commands 2019-09-17 22:18:58 +10:00
Connor McLaughlin b951f27381 CDROM: Stub implementation 2019-09-17 21:07:56 +10:00
Connor McLaughlin a0e7dff37c common: Add a FIFOQueue helper class 2019-09-17 19:22:23 +10:00
Connor McLaughlin 2128a2984b Add interrupt controller emulation 2019-09-17 16:26:00 +10:00
Connor McLaughlin c615e007c0 GPU: Serialization for CRTC state 2019-09-17 14:40:23 +10:00
Connor McLaughlin f47688b61f System: Basic timings for GPU scanout 2019-09-17 14:25:25 +10:00
Connor McLaughlin 9475c281bd Build: Set /MP on projects which are missing it 2019-09-17 14:25:17 +10:00
Connor McLaughlin 540f282213 CPU: Fix incorrect exception vector for break 2019-09-15 12:43:54 +10:00
Connor McLaughlin 5babc076f5 Bitfield: Fix incorrect shift in operator<<= 2019-09-15 12:42:43 +10:00
Connor McLaughlin d58dbe04c0 CPU: Fix load delay register reads for same register in delay slot 2019-09-15 12:16:51 +10:00
Connor McLaughlin 1bb794dd39 GPU: Use max vertex count based on buffer size 2019-09-15 01:18:58 +10:00
Connor McLaughlin a58b687352 GPU: Cap batch sizes at 1024 vertices, flush if exceeded 2019-09-15 01:13:23 +10:00
Connor McLaughlin 4ca3b4b570 CPU: Fix alignment exception on register indirect branch 2019-09-15 01:13:11 +10:00
Connor McLaughlin bea727bbe4 CPU: Fix BGEZAL with rs == ra 2019-09-15 01:02:35 +10:00
Connor McLaughlin 273f010d17 GPU: Use degenerate triangles to split strips and batch them 2019-09-15 00:17:43 +10:00
Connor McLaughlin 1c8e326624 GPU: Fix off-by-one in rectangle rendering 2019-09-14 23:50:34 +10:00
Connor McLaughlin 77b15d156d System: Periodically flush GPU 
Needs real timings...
 2019-09-14 23:50:24 +10:00