2019-09-11 04:01:19 +00:00
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#include "gpu.h"
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#include "YBaseLib/Log.h"
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2019-09-14 10:28:47 +00:00
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#include "common/state_wrapper.h"
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2019-09-11 04:59:41 +00:00
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#include "dma.h"
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2019-09-17 14:22:41 +00:00
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#include "interrupt_controller.h"
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2019-09-18 05:43:25 +00:00
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#include "stb_image_write.h"
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2019-09-13 16:07:31 +00:00
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#include "system.h"
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2019-09-20 13:40:19 +00:00
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#include "timers.h"
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2019-10-04 05:00:32 +00:00
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#include <imgui.h>
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2019-09-11 04:01:19 +00:00
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Log_SetChannel(GPU);
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GPU::GPU() = default;
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GPU::~GPU() = default;
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2019-09-20 13:40:19 +00:00
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bool GPU::Initialize(System* system, DMA* dma, InterruptController* interrupt_controller, Timers* timers)
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2019-09-11 04:01:19 +00:00
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{
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2019-09-12 14:18:13 +00:00
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m_system = system;
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2019-09-11 04:01:19 +00:00
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m_dma = dma;
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2019-09-17 14:22:41 +00:00
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m_interrupt_controller = interrupt_controller;
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2019-09-20 13:40:19 +00:00
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m_timers = timers;
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2019-09-11 04:01:19 +00:00
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return true;
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}
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void GPU::Reset()
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{
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SoftReset();
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}
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void GPU::SoftReset()
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{
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m_GPUSTAT.bits = 0x14802000;
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2019-10-04 10:33:37 +00:00
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m_drawing_area = {};
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m_drawing_offset = {};
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2019-09-17 04:25:25 +00:00
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m_crtc_state = {};
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m_crtc_state.regs.display_address_start = 0;
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m_crtc_state.regs.horizontal_display_range = 0xC60260;
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m_crtc_state.regs.vertical_display_range = 0x3FC10;
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2019-10-13 07:33:20 +00:00
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m_GP0_buffer.clear();
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2019-10-04 10:33:37 +00:00
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m_GPUREAD_buffer.clear();
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2019-09-25 14:15:21 +00:00
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m_render_state = {};
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2019-09-27 11:20:35 +00:00
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m_render_state.texture_page_changed = true;
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m_render_state.texture_color_mode_changed = true;
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2019-09-25 14:15:21 +00:00
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m_render_state.transparency_mode_changed = true;
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2019-09-13 16:07:31 +00:00
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UpdateGPUSTAT();
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2019-09-17 04:25:25 +00:00
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UpdateCRTCConfig();
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2019-09-11 04:59:41 +00:00
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}
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2019-09-14 10:28:47 +00:00
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bool GPU::DoState(StateWrapper& sw)
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{
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if (sw.IsReading())
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2019-10-04 10:33:37 +00:00
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{
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// perform a reset to discard all pending draws/fb state
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Reset();
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}
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2019-09-14 10:28:47 +00:00
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sw.Do(&m_GPUSTAT.bits);
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2019-09-25 14:15:21 +00:00
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2019-09-26 13:33:20 +00:00
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sw.Do(&m_render_state.texture_page_x);
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sw.Do(&m_render_state.texture_page_y);
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2019-09-25 14:15:21 +00:00
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sw.Do(&m_render_state.texture_palette_x);
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sw.Do(&m_render_state.texture_palette_y);
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sw.Do(&m_render_state.texture_color_mode);
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sw.Do(&m_render_state.transparency_mode);
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sw.Do(&m_render_state.texture_window_mask_x);
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sw.Do(&m_render_state.texture_window_mask_y);
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sw.Do(&m_render_state.texture_window_offset_x);
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sw.Do(&m_render_state.texture_window_offset_y);
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sw.Do(&m_render_state.texture_x_flip);
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sw.Do(&m_render_state.texture_y_flip);
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sw.Do(&m_render_state.texpage_attribute);
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sw.Do(&m_render_state.texlut_attribute);
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2019-10-05 13:25:06 +00:00
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sw.Do(&m_render_state.texture_window_value);
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2019-09-27 11:20:35 +00:00
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sw.Do(&m_render_state.texture_page_changed);
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sw.Do(&m_render_state.texture_color_mode_changed);
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2019-09-25 14:15:21 +00:00
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sw.Do(&m_render_state.transparency_mode_changed);
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2019-10-05 13:25:06 +00:00
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sw.Do(&m_render_state.texture_window_changed);
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2019-09-25 14:15:21 +00:00
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2019-09-26 13:33:20 +00:00
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sw.Do(&m_drawing_area.left);
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sw.Do(&m_drawing_area.top);
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sw.Do(&m_drawing_area.right);
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sw.Do(&m_drawing_area.bottom);
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2019-09-14 10:28:47 +00:00
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sw.Do(&m_drawing_offset.x);
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sw.Do(&m_drawing_offset.y);
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sw.Do(&m_drawing_offset.x);
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2019-09-17 04:40:23 +00:00
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sw.Do(&m_crtc_state.regs.display_address_start);
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sw.Do(&m_crtc_state.regs.horizontal_display_range);
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sw.Do(&m_crtc_state.regs.vertical_display_range);
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sw.Do(&m_crtc_state.horizontal_resolution);
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sw.Do(&m_crtc_state.vertical_resolution);
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sw.Do(&m_crtc_state.dot_clock_divider);
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sw.Do(&m_crtc_state.visible_horizontal_resolution);
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sw.Do(&m_crtc_state.visible_vertical_resolution);
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sw.Do(&m_crtc_state.ticks_per_scanline);
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sw.Do(&m_crtc_state.visible_ticks_per_scanline);
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sw.Do(&m_crtc_state.total_scanlines_per_frame);
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sw.Do(&m_crtc_state.fractional_ticks);
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sw.Do(&m_crtc_state.current_tick_in_scanline);
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sw.Do(&m_crtc_state.current_scanline);
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sw.Do(&m_crtc_state.in_hblank);
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sw.Do(&m_crtc_state.in_vblank);
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if (sw.IsReading())
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UpdateSliceTicks();
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2019-10-13 07:33:20 +00:00
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sw.Do(&m_GP0_buffer);
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2019-09-14 10:28:47 +00:00
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sw.Do(&m_GPUREAD_buffer);
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if (sw.IsReading())
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{
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2019-09-27 11:20:35 +00:00
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m_render_state.texture_page_changed = true;
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m_render_state.texture_color_mode_changed = true;
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2019-09-25 14:15:21 +00:00
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m_render_state.transparency_mode_changed = true;
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2019-10-05 13:25:06 +00:00
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m_render_state.texture_window_changed = true;
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2019-10-05 13:28:34 +00:00
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UpdateDrawingArea();
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2019-09-14 10:28:47 +00:00
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UpdateGPUSTAT();
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}
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2019-09-14 10:45:26 +00:00
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if (!sw.DoMarker("GPU-VRAM"))
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return false;
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if (sw.IsReading())
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{
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std::vector<u16> vram;
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sw.Do(&vram);
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UpdateVRAM(0, 0, VRAM_WIDTH, VRAM_HEIGHT, vram.data());
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}
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else
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{
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std::vector<u16> vram(VRAM_WIDTH * VRAM_HEIGHT);
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ReadVRAM(0, 0, VRAM_WIDTH, VRAM_HEIGHT, vram.data());
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sw.Do(&vram);
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}
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2019-09-14 10:28:47 +00:00
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return !sw.HasError();
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}
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2019-10-04 12:10:43 +00:00
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void GPU::ResetGraphicsAPIState() {}
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void GPU::RestoreGraphicsAPIState() {}
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2019-10-04 05:00:32 +00:00
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void GPU::UpdateSettings() {}
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2019-09-26 04:03:32 +00:00
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2019-09-13 16:07:31 +00:00
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void GPU::UpdateGPUSTAT()
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2019-09-11 04:59:41 +00:00
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{
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2019-09-13 16:07:31 +00:00
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m_GPUSTAT.ready_to_send_vram = !m_GPUREAD_buffer.empty();
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m_GPUSTAT.ready_to_recieve_cmd = m_GPUREAD_buffer.empty();
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m_GPUSTAT.ready_to_recieve_dma = m_GPUREAD_buffer.empty();
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bool dma_request;
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switch (m_GPUSTAT.dma_direction)
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{
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case DMADirection::Off:
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dma_request = false;
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break;
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case DMADirection::FIFO:
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dma_request = true; // FIFO not full/full
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break;
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case DMADirection::CPUtoGP0:
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dma_request = m_GPUSTAT.ready_to_recieve_dma;
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break;
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case DMADirection::GPUREADtoCPU:
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dma_request = m_GPUSTAT.ready_to_send_vram;
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break;
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default:
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dma_request = false;
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break;
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}
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m_GPUSTAT.dma_data_request = dma_request;
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m_dma->SetRequest(DMA::Channel::GPU, dma_request);
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2019-09-11 04:01:19 +00:00
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}
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u32 GPU::ReadRegister(u32 offset)
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{
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2019-09-11 04:59:41 +00:00
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switch (offset)
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2019-09-11 04:01:19 +00:00
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{
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2019-09-11 04:59:41 +00:00
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case 0x00:
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return ReadGPUREAD();
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case 0x04:
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2019-09-17 04:25:25 +00:00
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{
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// Bit 31 of GPUSTAT is always clear during vblank.
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u32 bits = m_GPUSTAT.bits;
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2019-10-15 12:36:10 +00:00
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bits &= ~(BoolToUInt32(m_crtc_state.in_vblank) << 31);
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2019-09-17 04:25:25 +00:00
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return bits;
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}
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2019-09-11 04:59:41 +00:00
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default:
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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return UINT32_C(0xFFFFFFFF);
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2019-09-11 04:01:19 +00:00
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}
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2019-09-11 04:59:41 +00:00
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}
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void GPU::WriteRegister(u32 offset, u32 value)
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{
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switch (offset)
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2019-09-11 04:01:19 +00:00
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{
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2019-09-11 04:59:41 +00:00
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case 0x00:
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WriteGP0(value);
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return;
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case 0x04:
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WriteGP1(value);
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return;
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default:
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Log_ErrorPrintf("Unhandled register write: %02X <- %08X", offset, value);
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return;
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2019-09-11 04:01:19 +00:00
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}
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2019-09-11 04:59:41 +00:00
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}
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2019-09-11 04:01:19 +00:00
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2019-10-13 06:48:11 +00:00
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void GPU::DMARead(u32* words, u32 word_count)
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2019-09-11 04:59:41 +00:00
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{
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if (m_GPUSTAT.dma_direction != DMADirection::GPUREADtoCPU)
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{
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Log_ErrorPrintf("Invalid DMA direction from GPU DMA read");
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2019-10-13 06:48:11 +00:00
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std::fill_n(words, word_count, UINT32_C(0xFFFFFFFF));
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return;
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}
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const u32 words_to_copy = std::min(word_count, static_cast<u32>(m_GPUREAD_buffer.size()));
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if (!m_GPUREAD_buffer.empty())
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{
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auto it = m_GPUREAD_buffer.begin();
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for (u32 i = 0; i < word_count; i++)
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words[i] = *(it++);
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m_GPUREAD_buffer.erase(m_GPUREAD_buffer.begin(), it);
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}
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if (words_to_copy < word_count)
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{
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Log_WarningPrintf("Partially-empty GPUREAD buffer on GPU DMA read");
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std::fill_n(words + words_to_copy, word_count - words_to_copy, u32(0));
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2019-09-11 04:59:41 +00:00
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}
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2019-10-13 06:48:11 +00:00
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UpdateGPUSTAT();
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2019-09-11 04:01:19 +00:00
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}
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2019-10-13 06:48:11 +00:00
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void GPU::DMAWrite(const u32* words, u32 word_count)
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2019-09-11 04:59:41 +00:00
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{
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2019-09-11 06:04:31 +00:00
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switch (m_GPUSTAT.dma_direction)
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{
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case DMADirection::CPUtoGP0:
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2019-10-13 06:48:11 +00:00
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{
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2019-10-18 12:05:06 +00:00
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#if 0
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2019-10-13 07:33:20 +00:00
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// partial command buffered? have to go through the slow path
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if (!m_GP0_buffer.empty())
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2019-10-13 06:48:11 +00:00
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{
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2019-10-13 07:33:20 +00:00
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std::copy(words, words + word_count, std::back_inserter(m_GP0_buffer));
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const u32* command_ptr = m_GP0_buffer.data();
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u32 command_size = static_cast<u32>(m_GP0_buffer.size());
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do
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{
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const u32* prev_command_ptr = command_ptr;
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const bool result = HandleGP0Command(command_ptr, command_size);
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command_size -= command_ptr - prev_command_ptr;
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if (!result)
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break;
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} while (command_size > 0);
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if (command_size > 0 && command_size < m_GP0_buffer.size())
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m_GP0_buffer.erase(m_GP0_buffer.begin(), m_GP0_buffer.begin() + (m_GP0_buffer.size() - command_size));
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else if (command_size == 0)
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m_GP0_buffer.clear();
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}
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else
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{
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// fast path - read directly from DMA buffer
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const u32* command_ptr = words;
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u32 command_size = word_count;
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do
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{
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const u32* prev_command_ptr = command_ptr;
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const bool result = HandleGP0Command(command_ptr, command_size);
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command_size -= command_ptr - prev_command_ptr;
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if (!result)
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break;
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} while (command_size > 0);
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if (command_size > 0)
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{
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// partial command left over
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std::copy(command_ptr, command_ptr + command_size, std::back_inserter(m_GP0_buffer));
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}
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2019-10-13 06:48:11 +00:00
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}
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UpdateGPUSTAT();
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2019-10-18 12:05:06 +00:00
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#else
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for (u32 i = 0; i < word_count; i++)
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WriteGP0(words[i]);
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#endif
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2019-10-13 06:48:11 +00:00
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}
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break;
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2019-09-11 06:04:31 +00:00
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default:
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2019-10-13 06:48:11 +00:00
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{
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Log_ErrorPrintf("Unhandled GPU DMA write mode %u for %u words",
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static_cast<u32>(m_GPUSTAT.dma_direction.GetValue()), word_count);
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}
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break;
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2019-09-11 06:04:31 +00:00
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}
|
2019-09-11 04:59:41 +00:00
|
|
|
}
|
|
|
|
|
2019-09-17 04:25:25 +00:00
|
|
|
void GPU::UpdateCRTCConfig()
|
|
|
|
{
|
|
|
|
static constexpr std::array<TickCount, 8> dot_clock_dividers = {{8, 4, 10, 5, 7, 7, 7, 7}};
|
|
|
|
static constexpr std::array<u32, 8> horizontal_resolutions = {{256, 320, 512, 630, 368, 368, 368, 368}};
|
|
|
|
static constexpr std::array<u32, 2> vertical_resolutions = {{240, 480}};
|
|
|
|
CRTCState& cs = m_crtc_state;
|
|
|
|
|
|
|
|
const u8 horizontal_resolution_index = m_GPUSTAT.horizontal_resolution_1 | (m_GPUSTAT.horizontal_resolution_2 << 2);
|
|
|
|
cs.dot_clock_divider = dot_clock_dividers[horizontal_resolution_index];
|
|
|
|
cs.horizontal_resolution = horizontal_resolutions[horizontal_resolution_index];
|
2019-10-15 12:36:10 +00:00
|
|
|
cs.vertical_resolution =
|
|
|
|
vertical_resolutions[BoolToUInt8(m_GPUSTAT.vertical_interlace && m_GPUSTAT.vertical_resolution)];
|
2019-09-17 04:25:25 +00:00
|
|
|
|
|
|
|
// check for a change in resolution
|
|
|
|
const u32 old_horizontal_resolution = cs.visible_horizontal_resolution;
|
|
|
|
const u32 old_vertical_resolution = cs.visible_vertical_resolution;
|
|
|
|
cs.visible_horizontal_resolution = std::max((cs.regs.X2 - cs.regs.X1) / cs.dot_clock_divider, u32(1));
|
|
|
|
cs.visible_vertical_resolution = cs.regs.Y2 - cs.regs.Y1 + 1;
|
|
|
|
if (cs.visible_horizontal_resolution != old_horizontal_resolution ||
|
|
|
|
cs.visible_vertical_resolution != old_vertical_resolution)
|
|
|
|
{
|
|
|
|
Log_InfoPrintf("Visible resolution is now %ux%u", cs.visible_horizontal_resolution, cs.visible_vertical_resolution);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (m_GPUSTAT.pal_mode)
|
|
|
|
{
|
|
|
|
cs.total_scanlines_per_frame = 314;
|
|
|
|
cs.ticks_per_scanline = 3406;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cs.total_scanlines_per_frame = 263;
|
|
|
|
cs.ticks_per_scanline = 3413;
|
|
|
|
}
|
|
|
|
|
|
|
|
UpdateSliceTicks();
|
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::UpdateSliceTicks()
|
2019-09-14 13:49:55 +00:00
|
|
|
{
|
2019-09-17 04:25:25 +00:00
|
|
|
// the next event is at the end of the next scanline
|
2019-09-26 14:03:28 +00:00
|
|
|
#if 1
|
2019-09-20 13:40:19 +00:00
|
|
|
const TickCount ticks_until_next_event = m_crtc_state.ticks_per_scanline - m_crtc_state.current_tick_in_scanline;
|
|
|
|
#else
|
2019-09-17 04:25:25 +00:00
|
|
|
// or at vblank. this will depend on the timer config..
|
|
|
|
const TickCount ticks_until_next_event =
|
|
|
|
((m_crtc_state.total_scanlines_per_frame - m_crtc_state.current_scanline) * m_crtc_state.ticks_per_scanline) -
|
|
|
|
m_crtc_state.current_tick_in_scanline;
|
2019-09-20 13:40:19 +00:00
|
|
|
#endif
|
2019-09-17 04:25:25 +00:00
|
|
|
|
|
|
|
// convert to master clock, rounding up as we want to overshoot not undershoot
|
|
|
|
const TickCount system_ticks = (ticks_until_next_event * 7 + 10) / 11;
|
2019-09-20 13:59:48 +00:00
|
|
|
m_system->SetDowncount(system_ticks);
|
2019-09-17 04:25:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::Execute(TickCount ticks)
|
|
|
|
{
|
|
|
|
// convert cpu/master clock to GPU ticks, accounting for partial cycles because of the non-integer divider
|
|
|
|
{
|
|
|
|
const TickCount temp = (ticks * 11) + m_crtc_state.fractional_ticks;
|
|
|
|
m_crtc_state.current_tick_in_scanline += temp / 7;
|
|
|
|
m_crtc_state.fractional_ticks = temp % 7;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (m_crtc_state.current_tick_in_scanline >= m_crtc_state.ticks_per_scanline)
|
|
|
|
{
|
|
|
|
m_crtc_state.current_tick_in_scanline -= m_crtc_state.ticks_per_scanline;
|
|
|
|
m_crtc_state.current_scanline++;
|
2019-09-20 13:40:19 +00:00
|
|
|
if (m_timers->IsUsingExternalClock(HBLANK_TIMER_INDEX))
|
|
|
|
m_timers->AddTicks(HBLANK_TIMER_INDEX, 1);
|
2019-09-17 04:25:25 +00:00
|
|
|
|
2019-09-26 14:03:28 +00:00
|
|
|
// past the end of vblank?
|
|
|
|
if (m_crtc_state.current_scanline >= m_crtc_state.total_scanlines_per_frame)
|
|
|
|
{
|
|
|
|
// flush any pending draws and "scan out" the image
|
|
|
|
FlushRender();
|
|
|
|
UpdateDisplay();
|
|
|
|
|
|
|
|
// start the new frame
|
|
|
|
m_system->IncrementFrameNumber();
|
|
|
|
m_crtc_state.current_scanline = 0;
|
|
|
|
|
2019-10-15 12:36:10 +00:00
|
|
|
if (m_GPUSTAT.vertical_interlace & m_GPUSTAT.vertical_resolution)
|
2019-09-26 14:03:28 +00:00
|
|
|
m_GPUSTAT.drawing_even_line ^= true;
|
|
|
|
}
|
|
|
|
|
2019-09-17 04:25:25 +00:00
|
|
|
const bool old_vblank = m_crtc_state.in_vblank;
|
2019-09-20 13:40:19 +00:00
|
|
|
const bool new_vblank = m_crtc_state.current_scanline >= m_crtc_state.visible_vertical_resolution;
|
|
|
|
if (new_vblank != old_vblank)
|
2019-09-17 04:25:25 +00:00
|
|
|
{
|
2019-09-20 13:40:19 +00:00
|
|
|
m_crtc_state.in_vblank = new_vblank;
|
|
|
|
|
|
|
|
if (!old_vblank)
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Now in v-blank");
|
|
|
|
m_interrupt_controller->InterruptRequest(InterruptController::IRQ::VBLANK);
|
|
|
|
}
|
|
|
|
|
|
|
|
m_timers->SetGate(HBLANK_TIMER_INDEX, new_vblank);
|
2019-09-17 04:25:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// alternating even line bit in 240-line mode
|
2019-10-15 12:36:10 +00:00
|
|
|
if (!(m_GPUSTAT.vertical_interlace & m_GPUSTAT.vertical_resolution))
|
2019-09-17 04:25:25 +00:00
|
|
|
m_GPUSTAT.drawing_even_line = ConvertToBoolUnchecked(m_crtc_state.current_scanline & u32(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
UpdateSliceTicks();
|
2019-09-14 13:49:55 +00:00
|
|
|
}
|
|
|
|
|
2019-09-11 04:59:41 +00:00
|
|
|
u32 GPU::ReadGPUREAD()
|
2019-09-11 04:01:19 +00:00
|
|
|
{
|
2019-09-13 16:07:31 +00:00
|
|
|
if (m_GPUREAD_buffer.empty())
|
|
|
|
{
|
2019-10-05 12:22:49 +00:00
|
|
|
Log_DevPrintf("GPUREAD read while buffer is empty");
|
2019-09-13 16:07:31 +00:00
|
|
|
return UINT32_C(0xFFFFFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
const u32 value = m_GPUREAD_buffer.front();
|
|
|
|
m_GPUREAD_buffer.pop_front();
|
|
|
|
UpdateGPUSTAT();
|
|
|
|
return value;
|
2019-09-11 04:01:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::WriteGP0(u32 value)
|
|
|
|
{
|
2019-10-13 07:33:20 +00:00
|
|
|
m_GP0_buffer.push_back(value);
|
|
|
|
Assert(m_GP0_buffer.size() <= 1048576);
|
|
|
|
|
|
|
|
const u32* command_ptr = m_GP0_buffer.data();
|
2019-10-18 12:05:06 +00:00
|
|
|
const u32 command = m_GP0_buffer[0] >> 24;
|
|
|
|
if ((this->*s_GP0_command_handler_table[command])(command_ptr, static_cast<u32>(m_GP0_buffer.size())))
|
2019-10-13 07:33:20 +00:00
|
|
|
{
|
|
|
|
DebugAssert((command_ptr - m_GP0_buffer.data()) == m_GP0_buffer.size());
|
|
|
|
m_GP0_buffer.clear();
|
|
|
|
}
|
|
|
|
|
2019-10-13 06:48:11 +00:00
|
|
|
UpdateGPUSTAT();
|
|
|
|
}
|
2019-09-11 06:04:31 +00:00
|
|
|
|
2019-09-11 04:01:19 +00:00
|
|
|
|
|
|
|
void GPU::WriteGP1(u32 value)
|
|
|
|
{
|
|
|
|
const u8 command = Truncate8(value >> 24);
|
2019-09-11 04:59:41 +00:00
|
|
|
const u32 param = value & UINT32_C(0x00FFFFFF);
|
|
|
|
switch (command)
|
|
|
|
{
|
2019-10-15 12:36:26 +00:00
|
|
|
case 0x00: // Reset GPU
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("GP1 reset GPU");
|
|
|
|
SoftReset();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-09-14 13:49:55 +00:00
|
|
|
case 0x01: // Clear FIFO
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("GP1 clear FIFO");
|
2019-10-15 12:36:26 +00:00
|
|
|
m_GP0_buffer.clear();
|
2019-09-14 13:49:55 +00:00
|
|
|
UpdateGPUSTAT();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-10-05 12:22:49 +00:00
|
|
|
case 0x02: // Acknowledge Interrupt
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Acknowledge interrupt");
|
|
|
|
m_GPUSTAT.interrupt_request = false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-09-11 04:59:41 +00:00
|
|
|
case 0x04: // DMA Direction
|
|
|
|
{
|
|
|
|
m_GPUSTAT.dma_direction = static_cast<DMADirection>(param);
|
|
|
|
Log_DebugPrintf("DMA direction <- 0x%02X", static_cast<u32>(m_GPUSTAT.dma_direction.GetValue()));
|
2019-09-13 16:07:31 +00:00
|
|
|
UpdateGPUSTAT();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x05: // Set display start address
|
|
|
|
{
|
2019-09-17 04:25:25 +00:00
|
|
|
m_crtc_state.regs.display_address_start = param & CRTCState::Regs::DISPLAY_ADDRESS_START_MASK;
|
|
|
|
Log_DebugPrintf("Display address start <- 0x%08X", m_crtc_state.regs.display_address_start);
|
2019-09-27 15:09:31 +00:00
|
|
|
m_system->IncrementInternalFrameNumber();
|
2019-09-17 04:25:25 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x06: // Set horizontal display range
|
|
|
|
{
|
|
|
|
m_crtc_state.regs.horizontal_display_range = param & CRTCState::Regs::HORIZONTAL_DISPLAY_RANGE_MASK;
|
|
|
|
Log_DebugPrintf("Horizontal display range <- 0x%08X", m_crtc_state.regs.horizontal_display_range);
|
|
|
|
UpdateCRTCConfig();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x07: // Set display start address
|
|
|
|
{
|
|
|
|
m_crtc_state.regs.vertical_display_range = param & CRTCState::Regs::VERTICAL_DISPLAY_RANGE_MASK;
|
|
|
|
Log_DebugPrintf("Vertical display range <- 0x%08X", m_crtc_state.regs.vertical_display_range);
|
|
|
|
UpdateCRTCConfig();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x08: // Set display mode
|
|
|
|
{
|
|
|
|
union GP1_08h
|
|
|
|
{
|
|
|
|
u32 bits;
|
|
|
|
|
|
|
|
BitField<u32, u8, 0, 2> horizontal_resolution_1;
|
2019-10-15 12:36:10 +00:00
|
|
|
BitField<u32, bool, 2, 1> vertical_resolution;
|
2019-09-17 04:25:25 +00:00
|
|
|
BitField<u32, bool, 3, 1> pal_mode;
|
|
|
|
BitField<u32, bool, 4, 1> display_area_color_depth;
|
|
|
|
BitField<u32, bool, 5, 1> vertical_interlace;
|
|
|
|
BitField<u32, bool, 6, 1> horizontal_resolution_2;
|
|
|
|
BitField<u32, bool, 7, 1> reverse_flag;
|
|
|
|
};
|
|
|
|
|
|
|
|
const GP1_08h dm{param};
|
|
|
|
m_GPUSTAT.horizontal_resolution_1 = dm.horizontal_resolution_1;
|
|
|
|
m_GPUSTAT.vertical_resolution = dm.vertical_resolution;
|
|
|
|
m_GPUSTAT.pal_mode = dm.pal_mode;
|
|
|
|
m_GPUSTAT.display_area_color_depth_24 = dm.display_area_color_depth;
|
|
|
|
m_GPUSTAT.vertical_interlace = dm.vertical_interlace;
|
|
|
|
m_GPUSTAT.horizontal_resolution_2 = dm.horizontal_resolution_2;
|
|
|
|
m_GPUSTAT.reverse_flag = dm.reverse_flag;
|
|
|
|
|
|
|
|
Log_DebugPrintf("Set display mode <- 0x%08X", dm.bits);
|
|
|
|
UpdateCRTCConfig();
|
2019-09-11 04:59:41 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-10-05 12:22:49 +00:00
|
|
|
case 0x10:
|
|
|
|
case 0x11:
|
|
|
|
case 0x12:
|
|
|
|
case 0x13:
|
|
|
|
case 0x14:
|
|
|
|
case 0x15:
|
|
|
|
case 0x16:
|
|
|
|
case 0x17:
|
|
|
|
case 0x18:
|
|
|
|
case 0x19:
|
|
|
|
case 0x1A:
|
|
|
|
case 0x1B:
|
|
|
|
case 0x1C:
|
|
|
|
case 0x1D:
|
|
|
|
case 0x1E:
|
|
|
|
case 0x1F:
|
|
|
|
{
|
2019-10-05 14:37:31 +00:00
|
|
|
HandleGetGPUInfoCommand(value);
|
2019-10-05 12:22:49 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-09-11 04:59:41 +00:00
|
|
|
default:
|
|
|
|
Log_ErrorPrintf("Unimplemented GP1 command 0x%02X", command);
|
|
|
|
break;
|
2019-10-05 12:22:49 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-05 14:37:31 +00:00
|
|
|
void GPU::HandleGetGPUInfoCommand(u32 value)
|
2019-10-05 12:22:49 +00:00
|
|
|
{
|
2019-10-05 14:37:31 +00:00
|
|
|
const u8 subcommand = Truncate8(value & 0x07);
|
2019-10-05 12:22:49 +00:00
|
|
|
switch (subcommand)
|
|
|
|
{
|
|
|
|
case 0x00:
|
|
|
|
case 0x01:
|
|
|
|
case 0x06:
|
|
|
|
case 0x07:
|
|
|
|
// leave GPUREAD intact
|
|
|
|
break;
|
|
|
|
|
2019-10-06 13:12:17 +00:00
|
|
|
case 0x02: // Get Texture Window
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Get texture window");
|
|
|
|
m_GPUREAD_buffer.push_back(m_render_state.texture_window_value);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x03: // Get Draw Area Top Left
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Get drawing area top left");
|
|
|
|
m_GPUREAD_buffer.push_back((m_drawing_area.left & UINT32_C(0b1111111111)) |
|
|
|
|
((m_drawing_area.top & UINT32_C(0b1111111111)) << 10));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x04: // Get Draw Area Bottom Right
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Get drawing area bottom right");
|
|
|
|
m_GPUREAD_buffer.push_back((m_drawing_area.right & UINT32_C(0b1111111111)) |
|
|
|
|
((m_drawing_area.bottom & UINT32_C(0b1111111111)) << 10));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x05: // Get Drawing Offset
|
|
|
|
{
|
|
|
|
Log_DebugPrintf("Get drawing offset");
|
|
|
|
m_GPUREAD_buffer.push_back((m_drawing_offset.x & INT32_C(0b11111111111)) |
|
|
|
|
((m_drawing_offset.y & INT32_C(0b11111111111)) << 11));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2019-10-05 12:22:49 +00:00
|
|
|
default:
|
|
|
|
Log_WarningPrintf("Unhandled GetGPUInfo(0x%02X)", ZeroExtend32(subcommand));
|
|
|
|
break;
|
2019-09-11 04:59:41 +00:00
|
|
|
}
|
2019-09-11 04:01:19 +00:00
|
|
|
}
|
2019-09-11 06:04:31 +00:00
|
|
|
|
2019-09-26 11:44:02 +00:00
|
|
|
void GPU::UpdateDisplay() {}
|
2019-09-13 16:07:31 +00:00
|
|
|
|
2019-10-04 12:10:43 +00:00
|
|
|
void GPU::UpdateDrawingArea() {}
|
|
|
|
|
2019-09-14 10:45:26 +00:00
|
|
|
void GPU::ReadVRAM(u32 x, u32 y, u32 width, u32 height, void* buffer) {}
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2019-09-18 05:54:57 +00:00
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void GPU::FillVRAM(u32 x, u32 y, u32 width, u32 height, u16 color) {}
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2019-09-14 06:43:39 +00:00
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2019-09-12 15:10:08 +00:00
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void GPU::UpdateVRAM(u32 x, u32 y, u32 width, u32 height, const void* data) {}
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2019-09-17 14:58:30 +00:00
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void GPU::CopyVRAM(u32 src_x, u32 src_y, u32 dst_x, u32 dst_y, u32 width, u32 height) {}
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2019-10-13 07:33:20 +00:00
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void GPU::DispatchRenderCommand(RenderCommand rc, u32 num_vertices, const u32* command_ptr) {}
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2019-09-12 02:53:04 +00:00
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2019-09-13 16:07:31 +00:00
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void GPU::FlushRender() {}
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2019-09-25 14:15:21 +00:00
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void GPU::RenderState::SetFromPolygonTexcoord(u32 texcoord0, u32 texcoord1)
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2019-09-13 16:07:31 +00:00
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{
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SetFromPaletteAttribute(Truncate16(texcoord0 >> 16));
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SetFromPageAttribute(Truncate16(texcoord1 >> 16));
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}
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2019-09-25 14:15:21 +00:00
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void GPU::RenderState::SetFromRectangleTexcoord(u32 texcoord)
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2019-09-13 16:07:31 +00:00
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{
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SetFromPaletteAttribute(Truncate16(texcoord >> 16));
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}
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2019-09-25 14:15:21 +00:00
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void GPU::RenderState::SetFromPageAttribute(u16 value)
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2019-09-13 16:07:31 +00:00
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{
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2019-09-25 14:15:21 +00:00
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const u16 old_page_attribute = texpage_attribute;
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2019-09-13 16:07:31 +00:00
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value &= PAGE_ATTRIBUTE_MASK;
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2019-09-25 14:15:21 +00:00
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if (texpage_attribute == value)
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2019-09-13 16:07:31 +00:00
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return;
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2019-09-27 11:20:35 +00:00
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texpage_attribute = value;
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2019-09-26 13:33:20 +00:00
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texture_page_x = static_cast<s32>(ZeroExtend32(value & UINT16_C(0x0F)) * UINT32_C(64));
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texture_page_y = static_cast<s32>(ZeroExtend32((value >> 4) & UINT16_C(1)) * UINT32_C(256));
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2019-09-27 11:20:35 +00:00
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texture_page_changed |=
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(old_page_attribute & PAGE_ATTRIBUTE_TEXTURE_PAGE_MASK) != (value & PAGE_ATTRIBUTE_TEXTURE_PAGE_MASK);
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const TextureColorMode old_color_mode = texture_color_mode;
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2019-09-25 14:15:21 +00:00
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texture_color_mode = (static_cast<TextureColorMode>((value >> 7) & UINT16_C(0x03)));
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if (texture_color_mode == TextureColorMode::Reserved_Direct16Bit)
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texture_color_mode = TextureColorMode::Direct16Bit;
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2019-09-27 11:20:35 +00:00
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texture_color_mode_changed |= old_color_mode != texture_color_mode;
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2019-09-18 14:55:06 +00:00
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2019-09-25 14:15:21 +00:00
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const TransparencyMode old_transparency_mode = transparency_mode;
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2019-09-18 14:55:06 +00:00
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transparency_mode = (static_cast<TransparencyMode>((value >> 5) & UINT16_C(0x03)));
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2019-09-25 14:15:21 +00:00
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transparency_mode_changed = old_transparency_mode != transparency_mode;
|
2019-09-13 16:07:31 +00:00
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}
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2019-09-25 14:15:21 +00:00
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void GPU::RenderState::SetFromPaletteAttribute(u16 value)
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2019-09-13 16:07:31 +00:00
|
|
|
{
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value &= PALETTE_ATTRIBUTE_MASK;
|
2019-09-25 14:15:21 +00:00
|
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if (texlut_attribute == value)
|
2019-09-13 16:07:31 +00:00
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|
return;
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|
2019-09-25 14:15:21 +00:00
|
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texture_palette_x = static_cast<s32>(ZeroExtend32(value & UINT16_C(0x3F)) * UINT32_C(16));
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texture_palette_y = static_cast<s32>(ZeroExtend32((value >> 6) & UINT16_C(0x1FF)));
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texlut_attribute = value;
|
2019-09-27 11:20:35 +00:00
|
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texture_page_changed = true;
|
2019-09-13 16:07:31 +00:00
|
|
|
}
|
2019-09-18 05:43:25 +00:00
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|
2019-10-05 13:25:06 +00:00
|
|
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void GPU::RenderState::SetTextureWindow(u32 value)
|
|
|
|
{
|
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|
|
value &= TEXTURE_WINDOW_MASK;
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|
|
if (texture_window_value == value)
|
|
|
|
return;
|
|
|
|
|
|
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|
texture_window_mask_x = value & UINT32_C(0x1F);
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|
texture_window_mask_y = (value >> 5) & UINT32_C(0x1F);
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|
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|
texture_window_offset_x = (value >> 10) & UINT32_C(0x1F);
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texture_window_offset_y = (value >> 15) & UINT32_C(0x1F);
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|
|
texture_window_value = value;
|
|
|
|
texture_window_changed = true;
|
|
|
|
}
|
|
|
|
|
2019-09-18 05:43:25 +00:00
|
|
|
bool GPU::DumpVRAMToFile(const char* filename, u32 width, u32 height, u32 stride, const void* buffer, bool remove_alpha)
|
|
|
|
{
|
|
|
|
std::vector<u32> rgba8_buf(width * height);
|
|
|
|
|
|
|
|
const char* ptr_in = static_cast<const char*>(buffer);
|
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|
|
u32* ptr_out = rgba8_buf.data();
|
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|
|
for (u32 row = 0; row < height; row++)
|
|
|
|
{
|
|
|
|
const char* row_ptr_in = ptr_in;
|
|
|
|
|
|
|
|
for (u32 col = 0; col < width; col++)
|
|
|
|
{
|
|
|
|
u16 src_col;
|
|
|
|
std::memcpy(&src_col, row_ptr_in, sizeof(u16));
|
|
|
|
row_ptr_in += sizeof(u16);
|
|
|
|
*(ptr_out++) = RGBA5551ToRGBA8888(remove_alpha ? (src_col | u16(0x8000)) : src_col);
|
|
|
|
}
|
|
|
|
|
|
|
|
ptr_in += stride;
|
|
|
|
}
|
|
|
|
return (stbi_write_png(filename, width, height, 4, rgba8_buf.data(), sizeof(u32) * width) != 0);
|
|
|
|
}
|
2019-10-12 12:15:38 +00:00
|
|
|
|
|
|
|
void GPU::DrawDebugWindows()
|
|
|
|
{
|
|
|
|
if (m_debug_options.show_state)
|
|
|
|
DrawDebugStateWindow();
|
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::DrawDebugMenu()
|
|
|
|
{
|
|
|
|
if (ImGui::BeginMenu("GPU"))
|
|
|
|
{
|
|
|
|
ImGui::MenuItem("Show State", nullptr, &m_debug_options.show_state);
|
|
|
|
ImGui::MenuItem("Show VRAM", nullptr, &m_debug_options.show_vram);
|
|
|
|
ImGui::MenuItem("Dump CPU to VRAM Copies", nullptr, &m_debug_options.dump_cpu_to_vram_copies);
|
|
|
|
ImGui::MenuItem("Dump VRAM to CPU Copies", nullptr, &m_debug_options.dump_vram_to_cpu_copies);
|
|
|
|
|
|
|
|
ImGui::EndMenu();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::DrawDebugStateWindow()
|
|
|
|
{
|
|
|
|
ImGui::SetNextWindowSize(ImVec2(450, 550), ImGuiCond_FirstUseEver);
|
|
|
|
if (!ImGui::Begin("GPU State", &m_debug_options.show_state))
|
|
|
|
{
|
|
|
|
ImGui::End();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ImGui::CollapsingHeader("CRTC", ImGuiTreeNodeFlags_DefaultOpen))
|
|
|
|
{
|
|
|
|
const auto& cs = m_crtc_state;
|
|
|
|
ImGui::Text("Resolution: %ux%u", cs.horizontal_resolution, cs.vertical_resolution);
|
|
|
|
ImGui::Text("Dot Clock Divider: %u", cs.dot_clock_divider);
|
|
|
|
ImGui::Text("Vertical Interlace: %s (%s field)", m_GPUSTAT.vertical_interlace ? "Yes" : "No",
|
|
|
|
m_GPUSTAT.interlaced_field ? "odd" : "even");
|
|
|
|
ImGui::Text("Display Enable: %s", m_GPUSTAT.display_enable ? "Yes" : "No");
|
|
|
|
ImGui::Text("Drawing Even Line: %s", m_GPUSTAT.drawing_even_line ? "Yes" : "No");
|
|
|
|
ImGui::NewLine();
|
|
|
|
|
|
|
|
ImGui::Text("Color Depth: %u-bit", m_GPUSTAT.display_area_color_depth_24 ? 24 : 15);
|
|
|
|
ImGui::Text("Start Offset: (%u, %u)", cs.regs.X.GetValue(), cs.regs.Y.GetValue());
|
|
|
|
ImGui::Text("Display Range: %u-%u, %u-%u", cs.regs.X1.GetValue(), cs.regs.X2.GetValue(), cs.regs.Y1.GetValue(),
|
|
|
|
cs.regs.Y2.GetValue());
|
|
|
|
ImGui::NewLine();
|
|
|
|
|
|
|
|
ImGui::Text("Visible Resolution: %ux%u", cs.visible_horizontal_resolution, cs.visible_vertical_resolution);
|
|
|
|
ImGui::Text("Ticks Per Scanline: %u (%u visible)", cs.ticks_per_scanline, cs.visible_ticks_per_scanline);
|
|
|
|
ImGui::Text("Scanlines Per Frame: %u", cs.total_scanlines_per_frame);
|
|
|
|
ImGui::Text("Current Scanline: %u (tick %u)", cs.current_scanline, cs.current_tick_in_scanline);
|
|
|
|
ImGui::Text("Horizontal Blank: %s", cs.in_hblank ? "Yes" : "No");
|
|
|
|
ImGui::Text("Vertical Blank: %s", cs.in_vblank ? "Yes" : "No");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ImGui::CollapsingHeader("GPU", ImGuiTreeNodeFlags_DefaultOpen))
|
|
|
|
{
|
|
|
|
ImGui::Text("Dither: %s", m_GPUSTAT.dither_enable ? "Enabled" : "Disabled");
|
|
|
|
ImGui::Text("Draw To Display Area: %s", m_GPUSTAT.dither_enable ? "Yes" : "No");
|
|
|
|
ImGui::Text("Draw Set Mask Bit: %s", m_GPUSTAT.draw_set_mask_bit ? "Yes" : "No");
|
|
|
|
ImGui::Text("Draw To Masked Pixels: %s", m_GPUSTAT.draw_to_masked_pixels ? "Yes" : "No");
|
|
|
|
ImGui::Text("Reverse Flag: %s", m_GPUSTAT.reverse_flag ? "Yes" : "No");
|
|
|
|
ImGui::Text("Texture Disable: %s", m_GPUSTAT.texture_disable ? "Yes" : "No");
|
|
|
|
ImGui::Text("PAL Mode: %s", m_GPUSTAT.pal_mode ? "Yes" : "No");
|
|
|
|
ImGui::Text("Interrupt Request: %s", m_GPUSTAT.interrupt_request ? "Yes" : "No");
|
|
|
|
ImGui::Text("DMA Request: %s", m_GPUSTAT.dma_data_request ? "Yes" : "No");
|
|
|
|
}
|
|
|
|
}
|